Motorola MCM63Z819TQ11, MCM63Z819TQ11R, MCM63Z819TQ15, MCM63Z819TQ15R, MCM63Z737TQ15 Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document by MCM63Z737/D

Advance Information

128K x 36 and 256K x 18 Bit

Flow±Through ZBT RAM

Synchronous Fast Static RAM

The ZBT RAM is a 4M±bit synchronous fast static RAM designed to provide zero bus turnaround. The ZBT RAM allows 100% use of bus cycles during back±to±back read/write and write/read cycles. The MCM63Z737 is organized as 128K words of 36 bits each and the MCM63Z819 is organized as 256K words of 18 bits each, fabricated with high performance silicon gate CMOS technology. This device integrates input registers, a 2±bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in communication applications. Synchronous design allows precise cycle control with the use of an external clock (CK). CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.

Addresses (SA), data inputs (DQ), and all control signals except output enable

(G) and linear burst order (LBO) are clock (CK) controlled through positive± edge±triggered noninverting registers.

Write cycles are internally self±timed and are initiated by the rising edge of the clock (CK) input. This feature eliminates complex off±chip write pulse generation and provides increased timing flexibility for incoming signals.

For read cycles, a flow±through SRAM allows output data to simply flow freely from the memory array.

•3.3 V LVTTL and LVCMOS Compatible

•MCM63Z737/MCM63Z819±11 = 11 ns Access/15 ns Cycle (66 MHz) MCM63Z737/MCM63Z819±15 = 15 ns Access/20 ns Cycle (50 MHz)

•Selectable Burst Sequencing Order (Linear/Interleaved)

•Internally Self±Timed Write Cycle

•Single±Cycle Deselect

•Byte Write Control

•ADV Controlled Burst

•100±Pin TQFP Package

MCM63Z737

MCM63Z819

TQ PACKAGE

TQFP

CASE 983A±01

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by Micron Technology, Inc. and Motorola, Inc.

This document contains information on a new product. Specifications and information herein are subject to change without notice.

2/6/98

MOTOROLA FAST SRAM	MCM63Z737 MCM63Z819
Motorola, Inc. 1998	D
	1

PIN ASSIGNMENT

SA SA SE1 SE2 SBd

SBc SBb SBa SE3

V

V CK SW CKE G

ADV NC NC SA SA

DD

SS

DQc		100 99 9897 9695 94 93 92 91 90 89 88 87 86 85 84 83 82 81
		1																							80													DQb
DQc
		2																							79													DQb
DQc
		3																							78													DQb
VDDQ		4																							77													VDDQ
VSS		5																							76													V
DQc		6																																				SS
																									75													DQb
DQc		7																							74													DQb
DQc
		8																							73													DQb
DQc		9																							72													DQb
VSS		10																							71													VSS
VDDQ		11																							70													V
DQc		12																																				DDQ
																									69													DQb
DQc
		13																							68													DQb
VSS		14
																									67													V
VDD		15																							66													SS
																																						V
VDD		16																																				SS
																									65													VDD
VSS		17																							64													V
DQd		18																																				SS
																									63													DQa
DQd
		19																							62													DQa
VDDQ		20																							61													VDDQ
VSS		21																							60													V
DQd		22																																				SS
																									59													DQa
DQd		23																							58													DQa
DQd		24																							57													DQa
DQd
		25																							56													DQa
VSS
		26																							55													V
VDDQ		27																																				SS
																									54													VDDQ
DQd		28																							53													DQa
DQd		29																							52													DQa
		30
DQd																									51													DQa
		31 32 33 34 35 36 3738 39 40 41 42 43 44 4546 4748 49 50
			LBO SA SA SA SA SA1 SA0																		SS		DD		NC NC SA SA SA SA SA SA SA
																	NC NC V					V

TOP VIEW

MCM63Z737

MCM63Z737DMCM63Z819	MOTOROLA FAST SRAM
2

PIN ASSIGNMENT

SA SA SE1 SE2 NC		NC SBb SBa SE3				V	V CK SW CKE			G ADV NC NC SA SA
						DD	SS

NC		100 99 9897 9695 94 93 92 91 90 89 88 87 86 85 84 83 82 81
		1																							80													SA
NC
		2																							79													NC
NC
		3																							78													NC
VDDQ		4																							77													VDDQ
VSS		5																							76													V
NC		6																																				SS
																									75													NC
NC		7																							74													DQa
DQb
		8																							73													DQa
DQb		9																							72													DQa
VSS		10																							71													VSS
VDDQ		11																							70													V
DQb		12																																				DDQ
																									69													DQa
DQb
		13																							68													DQa
VSS		14																							67													V
VDD		15																							66													SS
																																						V
VDD		16																																				SS
																									65													VDD
VSS		17																							64													V
DQb		18																																				SS
																									63													DQa
DQb
		19																							62													DQa
VDDQ		20																							61													VDDQ
VSS		21																							60													V
DQb		22																																				SS
																									59													DQa
DQb		23																							58													DQa
DQb		24																							57													NC
NC		25																							56													NC
VSS
		26																							55													V
VDDQ		27																																				SS
																									54													VDDQ
NC		28																							53													NC
NC		29																							52													NC
		30
NC																									51													NC
		31 32 33 34 35 36 3738 39 40 41 42 43 44 4546 4748 49 50
			LBO SA SA SA SA SA1 SA0																		SS		DD		NC NC SA SA SA SA SA SA SA
																	NC NC V					V

TOP VIEW

MCM63Z819

MOTOROLA FAST SRAM	MCM63Z737DMCM63Z819
	3

MCM63Z737 PIN DESCRIPTIONS

Pin Locations	Symbol	Type	Description
85	ADV	Input	Synchronous Load/Advance: Loads a new address into counter when
			low. RAM uses internally generated burst addresses when high.
89	CK	Input	Clock: This signal registers the address, data in, and all control signals
			except G and LBO.
87	CKE	Input	Clock Enable: Disables the CK input when CKE is high.
(a) 51, 52, 53, 56, 57, 58, 59, 62, 63	DQx	I/O	Synchronous Data I/O: ªxº refers to the byte being read or written
(b) 68, 69, 72, 73, 74, 75, 78, 79, 80			(byte a, b, c, d).
(c) 1, 2, 3, 6, 7, 8, 9, 12, 13
(d) 18, 19, 22, 23, 24, 25, 28, 29, 30
86	G	Input	Asynchronous Output Enable.
31	LBO	Input	Linear Burst Order Input: This pin must remain in steady state (this
			signal not registered or latched). It must be tied high or low.
			Low ± linear burst counter.
			High ± interleaved burst counter.
32, 33, 34, 35, 44, 45, 46,	SA	Input	Synchronous Address Inputs: These inputs are registered and must
47, 48, 49, 50, 81, 82, 99, 100			meet setup and hold times.
36, 37	SA0, SA1	Input	Synchronous Burst Address Inputs: The two LSB's of the address field.
			These pins must preset the burst address counter values. These inputs
			are registered and must meet setup and hold times.
93, 94, 95, 96	SBx	Input	Synchronous Byte Write Inputs: Enables write to byte ªxº
(a) (b) (c) (d)			(byte a, b, c, d) in conjunction with SW. Has no effect on read cycles.
98	SE1	Input	Synchronous Chip Enable: Active low to enable chip.
97	SE2	Input	Synchronous Chip Enable: Active high for depth expansion.
92	SE3	Input	Synchronous Chip Enable: Active low for depth expansion.
88	SW	Input	Synchronous Write: This signal writes only those bytes that have been
			selected using the byte write SBx pins.
15, 16, 41, 65, 91	VDD	Supply	Core Power Supply.
4, 11, 20, 27, 54, 61, 70, 77	VDDQ	Supply	I/O Power Supply.
5, 10, 14, 17, 21, 26, 40,	VSS	Supply	Ground.
55, 60, 64, 66, 67, 71, 76, 90
38, 39, 42, 43, 83, 84	NC	Ð	No Connection: There is no connection to the chip.

MCM63Z737DMCM63Z819	MOTOROLA FAST SRAM
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MCM63Z819 PIN DESCRIPTIONS

Pin Locations	Symbol	Type	Description
85	ADV	Input	Synchronous Load/Advance: Loads a new address into counter when
			low. RAM uses internally generated burst addresses when high.
89	CK	Input	Clock: This signal registers the address, data in, and all control signals
			except G and LBO.
87	CKE	Input	Clock Enable: Disables the CK input when CKE is high.
(a) 58, 59, 62, 63, 68, 69, 72, 73, 74	DQx	I/O	Synchronous Data I/O: ªxº refers to the byte being read or written
(b) 8, 9, 12, 13, 18, 19, 22, 23, 24			(byte a, b).
86	G	Input	Asynchronous Output Enable.
31	LBO	Input	Linear Burst Order Input: This pin must remain in steady state (this
			signal not registered or latched). It must be tied high or low.
			Low ± linear burst counter.
			High ± interleaved burst counter.
32, 33, 34, 35, 44, 45, 46,	SA	Input	Synchronous Address Inputs: These inputs are registered and must
47, 48, 49, 50, 80, 81, 82, 99, 100			meet setup and hold times.
36, 37	SA0, SA1	Input	Synchronous Burst Address Inputs: The two LSB's of the address field.
			These pins must preset the burst address counter values. These inputs
			are registered and must meet setup and hold times.
93, 94	SBx	Input	Synchronous Byte Write Inputs: Enables write to byte ªxº
(a) (b)			(byte a, b) in conjunction with SW. Has no effect on read cycles.
98	SE1	Input	Synchronous Chip Enable: Active low to enable chip.
97	SE2	Input	Synchronous Chip Enable: Active high for depth expansion.
92	SE3	Input	Synchronous Chip Enable: Active low for depth expansion.
88	SW	Input	Synchronous Write: This signal writes only those bytes that have been
			selected using the byte write SBx pins.
15, 16, 41, 65, 91	VDD	Supply	Core Power Supply.
4, 11, 20, 27, 54, 61, 70, 77	VDDQ	Supply	I/O Power Supply.
5, 10, 14, 17, 21, 26, 40,	VSS	Supply	Ground.
55, 60, 64, 66, 67, 71, 76, 90
1, 2, 3, 6, 7, 25, 28, 29, 30, 38,	NC	Ð	No Connection: There is no connection to the chip.
39, 42, 43, 51, 52, 53, 56, 57,
75, 78, 79, 83, 84, 95, 96

MOTOROLA FAST SRAM	MCM63Z737DMCM63Z819
	5

TRUTH TABLE

SA0 ±

Input Command

CK

CKE

E

SW

SBx

ADV

SAx

Next Operation

Code

Notes

L±H

1

X

X

X

X

X

Hold

H

1, 2

L±H

0

False

X

X

0

X

Deselect

D

1, 2

L±H

0

True

0

V

0

V

Load Address, New Write

W

1, 2, 3, 4, 5

L±H

0

True

1

X

0

V

Load Address, New Read

R

1, 2

L±H

0

X

X

V (W)

1

X

Burst

B

1, 2, 4,

6, 7

X (R, D)

Continue

NOTES:

1.X = don`t care, 1 = logic high, 0 = logic low, V = valid signal, according to AC Operating Conditions and Characteristics.

2.E = true if SE1 and SE3 = 0, and SE2 = 1.

3.Byte write enables, SBx, are evaluated only as new write addresses are loaded.

4.No control inputs except CKE, SBx, and ADV are recognized in a clock cycle where ADV is sampled high.

5.A write with SBx not valid does load addresses.

6.A burst write with SBx not valid does increment address.

7.ADV controls whether the RAM enters burst mode. If the previous cycle was a write, then ADV = 1 results in a burst write. If the previous cycle is a read, then ADV = 1 results in a burst read. ADV = 1 will also continue a deselect cycle.

WRITE TRUTH TABLE

										SBc	SBd
Cycle Type	SW			SBa				SBb		(See Note 1)	(See Note 1)
Read		H			X			X		X	X
Write Byte a		L			L			H		H	H
Write Byte b		L			H			L		H	H
Write Byte c (See Note 1)		L			H			H		L	H
Write Byte d (See Note 1)		L			H			H		H	L
Write All Bytes		L			L			L		L	L
NOTE:
1. Valid only for MCM63Z737.

LINEAR BURST ADDRESS TABLE (LBO = VSS)

1st Address (External)		2nd Address (Internal)		3rd Address (Internal)		4th Address (Internal)
X . . .	X00	X . . .	X01	X . . .	X10	X . . .	X11
X . . .	X01	X . . .	X10	X . . .	X11	X . . .	X00
X . . .	X10	X . . .	X11	X . . .	X00	X . . .	X01
X . . .	X11	X . . .	X00	X . . .	X01	X . . .	X10

INTERLEAVED BURST ADDRESS TABLE (LBO = VDD)

1st Address (External)		2nd Address (Internal)		3rd Address (Internal)		4th Address (Internal)
X . . .	X00	X . . .	X01	X . . .	X10	X . . .	X11
X . . .	X01	X . . .	X00	X . . .	X11	X . . .	X10
X . . .	X10	X . . .	X11	X . . .	X00	X . . .	X01
X . . .	X11	X . . .	X10	X . . .	X01	X . . .	X00

MCM63Z737DMCM63Z819	MOTOROLA FAST SRAM
6