Motorola MCM69F819ZP8R, MCM69F819ZP11R, MCM69F819ZP7.5, MCM69F819ZP8.5, MCM69F819TQ8.5R Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document by MCM69F819/D

256K x 18 Bit Flow±Through

BurstRAM Synchronous

Fast Static RAM

The MCM69F819 is a 4M bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the PowerPC and other high performance microprocessors. It is organized as 256K words of 18 bits each. This device integrates input registers, a 2±bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K).

Addresses (SA), data inputs (DQx), and all control signals except output enable (G) and linear burst order (LBO) are clock (K) controlled through positive± edge±triggered noninverting registers.

Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst addresses can be generated internally by the MCM69F819 (burst sequence operates in linear or interleaved mode dependent upon the state of LBO) and controlled by the burst address advance (ADV) input pin.

Write cycles are internally self±timed and are initiated by the rising edge of the clock (K) input. This feature eliminates complex off±chip write pulse generation and provides increased timing flexibility for incoming signals.

Synchronous byte write (SBx), synchronous global write (SGW), and synchronous write enable (SW) are provided to allow writes to either individual bytes or to all bytes. The two bytes are designated as ªaº and ªbº. SBacontrols DQa and SBb controls DQb. Individual bytes are written if the selected byte writes SBx are asserted with SW. All bytes are written if either SGW is asserted or if all SBx and SW are asserted.

For read cycles, a flow±through SRAM allows output data to simply flow freely from the memory array.

The MCM69F819 operates from a 3.3 V core power supply and all outputs operate on a 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC standard JESD8±5 compatible.

•MCM69F819±7.5: 7.5 ns Access/ 8.5 ns Cycle (117 MHz) MCM69F819±8: 8 ns Access/10 ns Cycle (100 MHz) MCM69F819±8.5: 8.5 ns Access/11 ns Cycle 90 MHz) MCM69F819±11: 11 ns Access/20 ns Cycle (50 MHz)

•3.3 V + 10%, ± 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply

•ADSP, ADSC, and ADV Burst Control Pins

•Selectable Burst Sequencing Order (Linear/Interleaved)

•Single±Cycle Deselect Timing

•Internally Self±Timed Write Cycle

•Byte Write and Global Write Control

•PB1 Version 2.0 Compatible

•JEDEC Standard 119±Pin PBGA and 100±Pin TQFP Packages

MCM69F819

ZP PACKAGE

PBGA

CASE 999±02

TQ PACKAGE

TQFP

CASE 983A±01

The PowerPC name is a trademark of IBM Corp., used under license therefrom.

REV 7 1/22/98

MOTOROLA FAST SRAM	MCM69F819
Motorola, Inc. 1998
	1

	FUNCTIONAL BLOCK DIAGRAM
LBO
ADV
K		BURST	2	18
ADSC	K2	COUNTER		256K x 18
		CLR
ADSP				ARRAY
		2
SA	ADDRESS	18	16
SA1
	REGISTER
SA0
SGW				18	18
SW	WRITE
	REGISTER
SBa	a
				2
	WRITE			DATA±IN
				REGISTER
	REGISTER
				K
	b
SBb
	K2
SE1	ENABLE
SE2
	REGISTER
SE3

G

DQa ± DQb

MCM69F819	MOTOROLA FAST SRAM
2

1	2	3	4	5	6	7
A	SA	SA		SA	SA
VDDQ			ADSP			VDDQ
B				SA	SE3	NC
NC	SE2	SA	ADSC
C	SA	SA	VDD	SA	SA	NC
NC
D		VSS		VSS		NC
DQb	NC		NC		DQa
E						DQa
NC	DQb	VSS	SE1	VSS	NC
F		VSS		VSS	DQa	VDDQ
VDDQ	NC		G
G			ADV	VSS	NC	DQa
NC	DQb	SBb
H		VSS		VSS	DQa	NC
DQb	NC		SGW
J	VDD		VDD		VDD	VDDQ
VDDQ		NC		NC
K		VSS		VSS		DQa
NC	DQb		K		NC
L			NC			NC
DQb	NC	VSS		SBa	DQa
M			SW	VSS		VDDQ
VDDQ	DQb	VSS			NC
N		VSS		VSS		NC
DQb	NC		SA1		DQa
P		VSS		VSS
NC	DQb		SA0		NC	DQa
R	SA	LBO	VDD	NC	SA	NC
NC
T	SA	SA		SA	SA	NC
NC			NC
U	NC	NC	NC	NC	NC	VDDQ
VDDQ

TOP VIEW 119 BUMP PBGA

PIN ASSIGNMENTS

SA SA SE1 SE2 NC

NC SBb SBa SE3

V

V K

SGW SW

G

ADSC

ADSP ADV SA SA

DD

SS

NC		100 99 9897 9695 94 93 92 91 90 89 88 87 86 85 84 83 82 81
		1																							80													SA
NC
		2																							79													NC
NC
		3																							78													NC
VDDQ		4																							77													VDDQ
VSS		5																							76													VSS
NC		6																							75													NC
NC
		7																							74													DQa
DQb
		8																							73													DQa
DQb
		9																							72													DQa
VSS		10
																									71													VSS
VDDQ		11																							70													VDDQ
DQb		12																							69													DQa
DQb		13																							68													DQa
NC		14																							67													VSS
VDD		15																							66													NC
NC		16																							65													VDD
VSS		17																							64													NC
DQb		18																							63													DQa
DQb
		19																							62													DQa
VDDQ
		20																							61													VDDQ
VSS		21																							60													V
DQb		22																																				SS
																									59													DQa
DQb
		23																							58													DQa
DQb		24
																									57													NC
NC		25																							56													NC
VSS
		26																							55													VSS
VDDQ		27																							54													V
NC		28																																				DDQ
																									53													NC
NC		29																							52													NC
		30
NC																									51													NC
		31 32 33 34 35 36 3738 39 40 41 42 43 444546 4748 49 50
			LBO SA SA SA SA SA1 SA0														NC NC V					V			NC NC SA SA SA SA SA SA SA
																					SS	DD

TOP VIEW 100 PIN TQFP

Not to Scale

MOTOROLA FAST SRAM	MCM69F819
	3

PBGA PIN DESCRIPTIONS

Pin Locations	Symbol	Type	Description
4B	ADSC	Input	Synchronous Address Status Controller: Active low, interrupts any
			ongoing burst and latches a new external address. Used to initiate a
			READ, WRITE, or chip deselect.
4A	ADSP	Input	Synchronous Address Status Processor: Active low, interrupts any
			ongoing burst and latches a new external address. Used to initiate a
			new READ, WRITE, or chip deselect (exception Ð chip deselect does
			not occur when ADSP is asserted and SE1 is high).
4G	ADV	Input	Synchronous Address Advance: Increments address count in
			accordance with counter type selected (linear/interleaved).
(a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P	DQx	I/O	Synchronous Data I/O: ªxº refers to the byte being read or written
(b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P			(byte a, b).
4F	G	Input	Asynchronous Output Enable Input:
			Low Ð enables output buffers (DQx pins).
			High Ð DQx pins are high impedance.
4K	K	Input	Clock: This signal registers the address, data in, and all control signals
			except G and LBO.
3R	LBO	Input	Linear Burst Order Input: This pin must remain in steady state (this
			signal not registered or latched). It must be tied high or low.
			Low Ð linear burst counter (68K/PowerPC).
			High Ð interleaved burst counter (486/i960/Pentium).
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C,	SA	Input	Synchronous Address Inputs: These inputs are registered and must
5C, 6C, 2R, 6R, 2T, 3T, 5T, 6T			meet setup and hold times.
4N, 4P	SA1, SA0	Input	Synchronous Address Inputs: These pins must be wired to the two
			LSBs of the address bus for proper burst operation. These inputs are
			registered and must meet setup and hold times.
5L, 3G	SBx	Input	Synchronous Byte Write Inputs: ªxº refers to the byte being written (byte
(a) (b)			a, b). SGW overrides SBx.
4E	SE1	Input	Synchronous Chip Enable: Active low to enable chip.
			Negated high Ð blocks ADSP or deselects chip when ADSC is
			asserted.
2B	SE2	Input	Synchronous Chip Enable: Active high for depth expansion.
6B	SE3	Input	Synchronous Chip Enable: Active low for depth expansion.
4H	SGW	Input	Synchronous Global Write: This signal writes all bytes regardless of the
			status of the SBx and SW signals. If only byte write signals SBx are
			being used, tie this pin high.
4M	SW	Input	Synchronous Write: This signal writes only those bytes that have been
			selected using the byte write SBx pins. If only byte write signals SBx
			are being used, tie this pin low.
4C, 2J, 4J, 6J, 4R	VDD	Supply	Core Power Supply.
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U	VDDQ	Supply	I/O Power Supply.
3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H,	VSS	Supply	Ground.
3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P
1B, 7B, 1C, 7C, 2D, 4D, 7D, 1E, 6E,	NC	Ð	No Connection: There is no connection to the chip.
2F, 1G, 6G, 2H, 7H, 3J, 5J, 1K, 6K,
2L, 4L, 7L, 6M, 2N, 7N, 1P, 6P, 1R,
5R, 7R, 1T, 4T, 7T, 2U, 3U, 4U, 5U, 6U

MCM69F819	MOTOROLA FAST SRAM
4

TQFP PIN DESCRIPTIONS

Pin Locations	Symbol	Type	Description
85	ADSC	Input	Synchronous Address Status Controller: Active low, interrupts any
			ongoing burst and latches a new external address. Used to initiate a
			READ, WRITE, or chip deselect.
84	ADSP	Input	Synchronous Address Status Processor: Active low, interrupts any
			ongoing burst and latches a new external address. Used to initiate a
			new READ, WRITE, or chip deselect (exception Ð chip deselect does
			not occur when ADSP is asserted and SE1 is high).
83	ADV	Input	Synchronous Address Advance: Increments address count in
			accordance with counter type selected (linear/interleaved).
(a) 58, 59, 62, 63, 68, 69, 72, 73, 74	DQx	I/O	Synchronous Data I/O: ªxº refers to the byte being read or written
(b) 8, 9, 12, 13, 18, 19, 22, 23, 24			(byte a, b).
86	G	Input	Asynchronous Output Enable Input:
			Low Ð enables output buffers (DQx pins).
			High Ð DQx pins are high impedance.
89	K	Input	Clock: This signal registers the address, data in, and all control signals
			except G and LBO.
31	LBO	Input	Linear Burst Order Input: This pin must remain in steady state (this
			signal not registered or latched). It must be tied high or low.
			Low Ð linear burst counter (68K/PowerPC).
			High Ð interleaved burst counter (486/i960/Pentium).
32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50,	SA	Input	Synchronous Address Inputs: These inputs are registered and must
80, 81, 82, 99, 100			meet setup and hold times.
36, 37	SA1, SA0	Input	Synchronous Address Inputs: These pins must be wired to the two
			LSBs of the address bus for proper burst operation. These inputs are
			registered and must meet setup and hold times.
93, 94	SBx	Input	Synchronous Byte Write Inputs: ªxº refers to the byte being written (byte
(a) (b)			a, b). SGW overrides SBx.
88	SGW	Input	Synchronous Global Write: This signal writes all bytes regardless of the
			status of the SBx and SW signals. If only byte write signals SBx are
			being used, tie this pin high.
98	SE1	Input	Synchronous Chip Enable: Active low to enable chip.
			Negated high Ð blocks ADSP or deselects chip when ADSC is
			asserted.
97	SE2	Input	Synchronous Chip Enable: Active high for depth expansion.
92	SE3	Input	Synchronous Chip Enable: Active low for depth expansion.
87	SW	Input	Synchronous Write: This signal writes only those bytes that have been
			selected using the byte write SBx pins. If only byte write signals SBx
			are being used, tie this pin low.
15, 41, 65, 91	VDD	Supply	Core Power Supply.
4, 11, 20, 27, 54, 61, 70, 77	VDDQ	Supply	I/O Power Supply.
5, 10, 17, 21, 26, 40,	VSS	Supply	Ground.
55, 60, 67, 71, 76, 90
1, 2, 3, 6, 7, 14, 16, 25, 28, 29, 30, 38,	NC	Ð	No Connection: There is no connection to the chip.
39, 42, 43, 51, 52, 53, 56, 57, 64, 66, 75,
78, 79, 95, 96

MOTOROLA FAST SRAM	MCM69F819
	5

TRUTH TABLE (See Notes 1 Through 5)

Address

3

Write 2, 4

Next Cycle

Used

SE1

SE2

SE3

ADSP

ADSC

ADV

G

DQx

Deselect

None

1

X

X

X

0

X

X

High±Z

X

Deselect

None

0

X

1

0

X

X

X

High±Z

X

Deselect

None

0

0

X

0

X

X

X

High±Z

X

Deselect

None

X

X

1

1

0

X

X

High±Z

X

Deselect

None

X

0

X

1

0

X

X

High±Z

X

Begin Read

External

0

1

0

0

X

X

0

High±Z

X5

Begin Read

External

0

1

0

1

0

X

0

High±Z

READ5

Continue Read

Next

X

X

X

1

1

0

1

High±Z

READ

Continue Read

Next

X

X

X

1

1

0

0

DQ

READ

Continue Read

Next

1

X

X

X

1

0

1

High±Z

READ

Continue Read

Next

1

X

X

X

1

0

0

DQ

READ

Suspend Read

Current

X

X

X

1

1

1

1

High±Z

READ

Suspend Read

Current

X

X

X

1

1

1

0

DQ

READ

Suspend Read

Current

1

X

X

X

1

1

1

High±Z

READ

Suspend Read

Current

1

X

X

X

1

1

0

DQ

READ

Begin Write

External

0

1

0

1

0

X

X

High±Z

WRITE

Continue Write

Next

X

X

X

1

1

0

X

High±Z

WRITE

Continue Write

Next

1

X

X

X

1

0

X

High±Z

WRITE

Suspend Write

Current

X

X

X

1

1

1

X

High±Z

WRITE

Suspend Write

Current

1

X

X

X

1

1

X

High±Z

WRITE

NOTES:

1.X = Don't Care. 1 = logic high. 0 = logic low.

2.Write is defined as either 1) any SBx and SW low or 2) SGW is low.

3.G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low.

4.On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must also remain negated at the completion of the write cycle to ensure proper write data hold times.

5.This read assumes the RAM was previously deselected.

LINEAR BURST ADDRESS TABLE (LBO = VSS)

1st Address (External)		2nd Address (Internal)		3rd Address (Internal)		4th Address (Internal)
X . . .	X00	X . . .	X01	X . . .	X10	X . . .	X11
X . . .	X01	X . . .	X10	X . . .	X11	X . . .	X00
X . . .	X10	X . . .	X11	X . . .	X00	X . . .	X01
X . . .	X11	X . . .	X00	X . . .	X01	X . . .	X10

INTERLEAVED BURST ADDRESS TABLE (LBO = VDD)

1st Address (External)		2nd Address (Internal)		3rd Address (Internal)		4th Address (Internal)
X . . .	X00	X . . .	X01	X . . .	X10	X . . .	X11
X . . .	X01	X . . .	X00	X . . .	X11	X . . .	X10
X . . .	X10	X . . .	X11	X . . .	X00	X . . .	X01
X . . .	X11	X . . .	X10	X . . .	X01	X . . .	X00

WRITE TRUTH TABLE

Cycle Type	SGW	SW	SBa	SBb
Read	H	H	X	X
Read	H	L	H	H
Write Byte a	H	L	L	H
Write Byte b	H	L	H	L
Write All Bytes	H	L	L	L
Write All Bytes	L	X	X	X

MCM69F819	MOTOROLA FAST SRAM
6