Motorola MCM6706ARJ6R2, MCM6706ARJ6, MCM6706ARJ7R2, MCM6706ARJ8, MCM6706ARJ8R2 Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document by MCM6706AR/D

32K x 8 Bit Static Random

Access Memory

The MCM6706AR is a 262,144 bit static random access memory organized as 32,768 words of 8 bits, fabricated using high performance silicon±gate BiCMOS technology. Static design eliminates the need for external clocks or timing strobes.

Output enable (G) is a special control feature that provides increased system flexibility and eliminates bus contention problems.

The MCM6706AR meets JEDEC standards and is available in a revolutionary pinout 300 mil, 32±lead surface±mount SOJ package.

•Single 5.0 V ± 10% Power Supply

•Fully Static Ð No Clock or Timing Strobes Necessary

•All Inputs and Outputs Are TTL Compatible

•Three State Outputs

•Fast Access Times: MCM6706AR±6 = 6 ns

MCM6706AR±7 = 7 ns MCM6706AR±8 = 8 ns

• Center Power and I/O Pins for Reduced Noise

	BLOCK DIAGRAM
A
A						VCC
						VSS
A
A			MEMORY
	ROW
A			MATRIX
A	DECODER	512 ROWS x 64 x 8
			COLUMNS
A
A
A
DQ0		COLUMN I/O
	INPUT	COLUMN DECODER
	DATA
	CONTROL
DQ7	A	A	A	A	A	A
E
W
G

MCM6706AR

J PACKAGE 300 MIL SOJ CASE 857±02

PIN ASSIGNMENT

A0				1	32			NC
A1				2	31		A14
A2				3	30		A13
A3							A12
				4	29
								G
		E		5	28
DQ0				6	27			DQ7
DQ1				7	26		DQ6
VCC				8	25		VSS
VSS				9	24		VCC
DQ2				10	23		DQ5
DQ3				11	22			DQ4
							A11
	W			12	21
A4				13	20		A10
A5				14	19		A9
A6				15	18		A8
A7				16	17			NC

PIN NAMES

A0 ± A14 . . . . . . . . . . . . . . . . . . . . . . . Address

W . . . . . . . . . . . . . . . . . . . . . . . . . Write Enable

E . . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable

G . . . . . . . . . . . . . . . . . . . . . . . Output Enable

DQ0 ± DQ7 . . . . . . . . . . . . Data Input/Output

VCC . . . . . . . . . . . . . . . . + 5 V Power Supply

VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground

NC . . . . . . . . . . . . . . . . . . . . . . No Connection

5/95

Motorola, Inc. 1995

TRUTH TABLE

	E		G			W			Mode	I/O Pin	Cycle
H				X			X		Not Selected	High±Z	Ð
	L			H			H		Read	High±Z	Ð
	L			L			H		Read	Dout	Read Cycle
	L			X			L		Write	Din	Write Cycle

ABSOLUTE MAXIMUM RATINGS (See Note)

Rating	Symbol	Value		Unit
Power Supply Voltage	VCC	± 0.5 to +	7.0	V
Voltage Relative to VSS for Any Pin	Vin, Vout	± 0.5 to VCC + 0.5		V
Except VCC
Output Current	Iout	± 30		mA
Power Dissipation	PD	2.0		W
Temperature Under Bias	Tbias	± 10 to +	85	°C
Operating Temperature	TA	0 to + 70		°C
Storage Temperature Ð Plastic	Tstg	± 55 to + 125		°C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high±impedance circuit.

This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.

DC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS

Parameter

Symbol

Min

Typ

Max

Unit

Supply Voltage (Operating Voltage Range)

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.2

Ð

VCC + 0.3*

V

Input Low Voltage

VIL

± 0.5**

Ð

0.8

V

*VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 2.0 ns) or I ≤ 30.0 mA.

** VIL (min) = ± 0.5 V dc @ 30.0 mA; VIL (min) = ± 2.0 V ac (pulse width ≤ 2.0 ns) or I ≤ 30.0 mA.

DC CHARACTERISTICS

Parameter

Symbol

Min

Max

Unit

Input Leakage Current (All Inputs, Vin = 0 to VCC)

Ilkg(I)

Ð

± 1.0

μA

Ilkg(O)

± 1.0

μA

Output Leakage Current (E

= VIH or G = VIH, Vout = 0 to VCC)

Ð

Output High Voltage (IOH = ± 4.0 mA)

VOH

2.4

Ð

V

Output Low Voltage (IOL = + 8.0 mA)

VOL

Ð

0.4

V

POWER SUPPLY CURRENTS

Parameter

Symbol

±6

±7

±8

Unit

Notes

AC Active Supply Current (Iout = 0 mA, VCC = max, f = fmax)

ICCA

235

225

215

mA

1, 2, 3

= VIH, VCC = max, f = fmax)

ISB1

AC Standby Current (E

95

85

75

mA

1, 2, 3

CMOS Standby Current (VCC = max, f = 0 MHz,

ISB2

20

20

20

mA

E

≥ VCC ± 0.2 V, Vin ≤ VSS, or ≥ VCC ± 0.2 V)

NOTES:

1.Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V, VIH = 3.0 V).

2.All addresses transition simultaneously low (LSB) and then high (MSB).

3.Data states are all zero.

MCM6706AR	MOTOROLA FAST SRAM
2

CAPACITANCE (f = 1.0 MHz, dV = 3.0							V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
							Parameter		Symbol	Max	Unit
Address Input Capacitance									Cin	5	pF
Control Pin Input Capacitance									Cin	6	pF
	(E,		G, W)
I/O Capacitance									Cout	6	pF

AC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level . . . . . . .	. . . . . . . . 1.5 V			Output Timing Measurement Reference Level								.	. . . . .	. .	.	. . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 0 to 3.0 V			Output Load . . .			. .	. . . . . . . .	. . . . . . .	.	. . . . . . . .	.	. . . .	See Figure 1A
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . 2 ns
READ CYCLE (See Notes 1 and 2)
				±6			±7			±8
Parameter	Symbol		Min		Max	Min		Max	Min		Max		Unit			Notes
Read Cycle Time	tAVAV		6		Ð	7		Ð	8		Ð		ns			3
Address Access Time	tAVQV		Ð		6	Ð		7	Ð		8		ns
Chip Enable Access Time	tELQV		Ð		6	Ð		7	Ð		8		ns
Output Enable Access Time	tGLQV		Ð		4	Ð		4	Ð		4		ns
Output Hold from Address Change	tAXQX		2.5		Ð	2.5		Ð	2.5		Ð		ns
Chip Enable Low to Output Active	tELQX		3		Ð	3		Ð	3		Ð		ns			4 ,5, 6
Chip Enable High to Output High±Z	tEHQZ		0		3	0		3.5	0		3.5		ns			4, 5, 6
Output Enable Low to Output Active	tGLQX		0		Ð	0		Ð	0		Ð		ns			4, 5, 6
Output Enable High to Output High±Z	tGHQZ		0		3	0		3.5	0		3.5		ns			4, 5, 6
NOTES:

1.W is high for read cycle.

2.Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles.

3.All read cycle timing is referenced from the last valid address to the first transitioning address.

4.At any given voltage and temperature, tEHQZ max < tELQX min, and tGHQZ max < tGLQX min, both for a given device and from device to device.

5.Transition is measured 200 mV from steady±state voltage with load of Figure 1B.

6.This parameter is sampled and not 100% tested.

7.Device is continuously selected (E = VIL, G = VIL).

8.Addresses valid prior to or coincident with E going low.

		AC TEST LOADS
				+5 V
	OUTPUT			480 Ω
			OUTPUT
	Z0 = 50 Ω	RL = 50 Ω
			255 Ω	5 pF
		VL = 1.5 V
	Figure 1A			Figure 1B

TIMING LIMITS

The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.

MOTOROLA FAST SRAM	MCM6706AR
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