Motorola MCM69R820AZP7, MCM69R820AZP7R, MCM69R820AZP8, MCM69R738AZP8, MCM69R738AZP6 Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document by MCM69R738A/D

Advance Information

4M Late Write 2.5 V I/O

The MCM69R738A/820A is a 4 megabit synchronous late write fast static RAM designed to provide high performance in secondary cache and ATM switch, Telecom, and other high speed memory applications. The MCM69R820A organized as 256K words by 18 bits, and the MCM69R738A organized as 128K words by 36 bits wide are fabricated in Motorola's high performance silicon gate BiCMOS technology.

The differential CK clock inputs control the timing of read/write operations of the RAM. At the rising edge of the CK clock all addresses, write enables, and synchronous selects are registered. An internal buffer and special logic enable the memory to accept write data on the rising edge of the CK clock a cycle after address and control signals. Read data is driven on the rising edge of the CK clock also.

The RAM uses 2.5 V inputs and outputs.

The synchronous write and byte enables allow writing to individual bytes or the entire word.

•Byte Write Control

•Single 3.3 V +10%, ± 5% Operation

•2.5 V I/O (VDDQ)

•Register to Register Synchronous Operation

•Asynchronous Output Enable

•Boundary Scan (JTAG) IEEE 1149.1 Compatible

•Differential Clock Inputs

•Optional x 18 or x 36 organization

•MCM69R738A/820A±5 = 5 ns MCM69R738A/820A±6 = 6 ns MCM69R738A/820A±7 = 7 ns MCM69R738A/820A±8 = 8 ns

•Sleep Mode Operation (ZZ Pin)

•119 Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array (PBGA) Package

MCM69R738A

MCM69R820A

ZP PACKAGE

PBGA

CASE 999±01

This document contains information on a new product. Specifications and information herein are subject to change without notice.

REV 1 8/13/97

MOTOROLA FAST SRAM	MCM69R738A MCM69R820A
Motorola, Inc. 1997	•
	1

FUNCTIONAL BLOCK DIAGRAM

ADDRESS

MEMORY

DATA IN

SA

REGISTER

REGISTERS

ARRAY

DQ

DATA OUT

REGISTER

SW

SW

CONTROL

SBx

REGISTERS

LOGIC

CK

G

SS

SS

REGISTERS

PIN ASSIGNMENTS

MCM69R738A

TOP VIEW

MCM69R820A

1

2

3

4

5

6

7

1

2

3

4

5

6

7

	A	VDDQ	SA	SA	NC	SA	SA	VDDQ
	B	NC	NC	SA	NC	SA	NC	NC
	C	NC	SA	SA	VDD	SA	SA	NC
	D
		DQc	DQc	VSS	NC	VSS	DQb	DQb
	E
		DQc	DQc	VSS	SS	VSS	DQb	DQb
	F	VDDQ	DQc	VSS	G	VSS	DQb	VDDQ
	G
		DQc	DQc	SBc	NC	SBb	DQb	DQb
	H	DQc	DQc	VSS	NC	VSS	DQb	DQb
	J	VDDQ	VDD	NC	VDD	NC	VDD	VDDQ
	K	DQd	DQd	VSS	CK	VSS	DQa	DQa
	L	DQd	DQd	SBd	CK	SBa	DQa	DQa
	M	VDDQ	DQd	VSS	SW	VSS	DQa	VDDQ
	N
		DQd	DQd	VSS	SA	VSS	DQa	DQa
	P
		DQd	DQd	VSS	SA	VSS	DQa	DQa
	R	NC	SA	VSS	VDD	VDD	SA	NC
	T
		NC	NC	SA	SA	SA	NC	ZZ
	U	VDDQ	TMS	TDI	TCK	TDO	NC	VDDQ

A						VDDQ
VDDQ	SA	SA	NC	SA	SA
B	NC	SA	NC	SA	NC	NC
NC
C	SA	SA	VDD	SA	SA	NC
NC
D		VSS		VSS		NC
DQb	NC		NC		DQa
E						DQa
NC	DQb	VSS	SS	VSS	NC
F		VSS		VSS		VDDQ
VDDQ	NC		G		DQa
G				VSS		DQa
NC	DQb	SBb	NC		NC
H		VSS		VSS		NC
DQb	NC		NC		DQa
J	VDD		VDD		VDD	VDDQ
VDDQ		NC		NC
K		VSS		VSS		DQa
NC	DQb		CK		NC
L		VSS	CK			NC
DQb	NC			SBa	DQa
M			SW	VSS		VDDQ
VDDQ	DQb	VSS			NC
N		VSS		VSS		NC
DQb	NC		SA		DQa
P		VSS		VSS
NC	DQb		SA		NC	DQa
R	SA	VSS	VDD	VDD	SA	NC
NC
T	SA	SA		SA	SA	ZZ
NC			NC
U						VDDQ
VDDQ	TMS	TDI	TCK	TDO	NC

MCM69R738A•MCM69R820A	MOTOROLA FAST SRAM
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MCM69R738A PIN DESCRIPTIONS

PBGA Pin Locations	Symbol	Type	Description
4K	CK	Input	Address, data in and control input register clock. Active high.
4L	CK	Input	Address, data in and control input register clock. Active low.
(a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P	DQx	I/O	Synchronous Data I/O.
(b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H
(c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H
(d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P
4F	G	Input	Output Enable: Asynchronous pin, active low.
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C,	SA	Input	Synchronous Address Inputs: Registered on the rising clock edge.
5C, 6C, 4N, 4P, 2R, 6R, 3T, 4T, 5T
5L, 5G, 3G, 3L	SBx	Input	Synchronous Byte Write Enable: Enables writes to byte x in
(a), (b), (c), (d)			conjunction with the SW input. Has no effect on read cycles, active
			low.
4E	SS	Input	Synchronous Chip Enable: Registered on the rising clock edge, active
			low.
4M	SW	Input	Synchronous Write: Registered on the rising clock edge, active low.
			Writes all enabled bytes.
4U	TCK	Input	Test Clock (JTAG).
3U	TDI	Input	Test Data In (JTAG).
5U	TDO	Output	Test Data Out (JTAG).
2U	TMS	Input	Test Mode Select (JTAG).
7T	ZZ	Input	Enables sleep mode, active high.
4C, 2J, 4J, 6J, 4R, 5R	VDD	Supply	Core Power Supply.
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U	VDDQ	Supply	Output Power Supply: provides operating power for output buffers.
3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H,	VSS	Supply	Ground.
3K, 5K, 3M, 5M, 3N, 5N, 3P, 5P, 3R
4A, 1B, 2B, 4B, 6B, 7B, 1C, 7C, 4D,	NC	Ð	No Connection: There is no connection to the chip.
4G, 4H, 3J, 5J, 1R, 7R, 1T, 2T, 6T, 6U			Note: 3J and 5J are tied common.

MOTOROLA FAST SRAM	MCM69R738A•MCM69R820A
	3

MCM69R820A PIN DESCRIPTIONS

PBGA Pin Locations	Symbol	Type	Description
4K	CK	Input	Address, data in and control input register clock. Active high.
4L	CK	Input	Address, data in and control input register clock. Active low.
(a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P	DQx	I/O	Synchronous Data I/O.
(b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P
4F	G	Input	Output Enable: Asynchronous pin, active low.
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C,	SA	Input	Synchronous Address Inputs: Registered on the rising clock edge.
6C, 4N, 4P, 2R, 6R, 2T, 3T, 5T, 6T
5L, 3G	SBx	Input	Synchronous Byte Write Enable: Enables writes to byte x in
(a), (b)			conjunction with the SW input. Has no effect on read cycles, active
			low.
4E	SS	Input	Synchronous Chip Enable: Registered on the rising clock edge, active
			low.
4M	SW	Input	Synchronous Write: Registered on the rising clock edge, active low.
			Writes all enabled bytes.
4U	TCK	Input	Test Clock (JTAG).
3U	TDI	Input	Test Data In (JTAG).
5U	TDO	Output	Test Data Out (JTAG).
2U	TMS	Input	Test Mode Select (JTAG).
7T	ZZ	Input	Enables sleep mode, active high.
4C, 2J, 4J, 6J, 4R, 5R	VDD	Supply	Core Power Supply.
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U	VDDQ	Supply	Output Power Supply: provides operating power for output buffers.
3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H,	VSS	Supply	Ground.
3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P, 3R
4A, 1B, 2B, 4B, 6B, 7B, 1C, 7C,	NC	Ð	No Connection: There is no connection to the chip.
2D, 4D, 7D, 1E, 6E, 2F, 1G, 4G, 6G,			Note: 3J and 5J are tied common.
2H, 4H, 7H, 3J, 5J, 1K, 6K, 2L, 7L, 6M, 2N,
7N, 1P, 6P, 1R, 7R, 1T, 4T, 6U

MCM69R738A•MCM69R820A	MOTOROLA FAST SRAM
4

ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS, See Note 1)

Rating	Symbol	Value	Unit
Core Supply Voltage	VDD	± 0.5 to + 4.6	V
Output Supply Voltage	VDDQ	± 0.5 to VDD + 0.5	V
Voltage On Any Pin	Vin	± 0.5 to VDD + 0.5	V
Input Current (per I/O)	Iin	± 50	mA
Output Current (per I/O)	Iout	± 70	mA
Power Dissipation (See Note 2)	PD	Ð	W
Operating Temperature	TA	0 to + 70	°C
Temperature Under Bias	Tbias	±10 to + 85	°C
Storage Temperature	Tstg	± 55 to + 125	°C
NOTES:

1.Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

2.Power dissipation capability will be dependent upon package characteristics and use environment. See enclosed thermal impedance data.

PBGA PACKAGE THERMAL CHARACTERISTICS

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high±impedance circuit.

This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established.

This device contains circuitry that will ensure the output devices are in High±Z at power up.

Rating		Symbol	Max	Unit	Notes
Junction to Ambient (Still Air)		RθJA	53	°C/W	1, 2
Junction to Ambient (@200 ft/min)	Single Layer Board	RθJA	38	°C/W	1, 2
Junction to Ambient (@200 ft/min)	Four Layer Board	RθJA	22	°C/W
Junction to Board (Bottom)		RθJB	14	°C/W	3
Junction to Case (Top)		RθJC	5	°C/W	4
NOTES:

1.Junction temperature is a function of on±chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

2.Per SEMI G38±87.

3.Indicates the average thermal resistance between the die and the printed circuit board.

4.Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC±883 Method 1012.1).

CLOCK TRUTH TABLE

K	ZZ	SS	SW	SBa	SBb	SBc	SBd	DQ (n)	DQ (n+1)	Mode
L ± H	L	L	H	X	X	X	X	X	Dout 0±35	Read Cycle All Bytes
L ± H	L	L	L	L	H	H	H	High±Z	Din 0±8	Write Cycle 1st Byte
L ± H	L	L	L	H	L	H	H	High±Z	Din 9±17	Write Cycle 2nd Byte
L ± H	L	L	L	H	H	L	H	High±Z	Din 18±26	Write Cycle 3rd Byte
L ± H	L	L	L	H	H	H	L	High±Z	Din 27±35	Write Cycle 4th Byte
L ± H	L	L	L	L	L	L	L	High±Z	Din 0±35	Write Cycle All Bytes
L ± H	L	L	L	H	H	H	H	High±Z	High±Z	Abort Write Cycle
L ± H	L	H	H	X	X	X	X	X	High±Z	Deselect Cycle
L ± H	L	H	L	X	X	X	X	High±Z	High±Z	Deselect Cycle
X	H	X	X	X	X	X	X	High±Z	High±Z	Sleep Mode

MOTOROLA FAST SRAM	MCM69R738A•MCM69R820A
	5

DC OPERATING CONDITIONS AND CHARACTERISTICS

(0°C ≤ TA ≤ 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS (See Notes 1 through 4)

				Typical	Typical	Typical	Typical
Parameter		Symbol	Min	±5	±6	±7	±8	Max	Unit	Notes
Core Power Supply Voltage		VDD	3.15	Ð	Ð	Ð	Ð	3.6	V
Output Driver Supply Voltage		VDDQ	2.3	Ð	Ð	Ð	Ð	2.7	V
Active Power Supply Current	(x18)	IDD1	Ð	390	360	330	320	490	mA	5
	(x36)		Ð	450	420	390	370	550
Quiescent Active Power Supply Current)		IDD2	Ð	180	180	180	180	250	mA	6, 10
Active Standby Power Supply Current)		ISB1	Ð	170	170	170	170	250	mA	7
Quiescent Standby Power Supply Current		ISB2	Ð	150	150	150	150	230	mA	8, 10
Sleep Mode Power Supply Current		ISB3	Ð	30	30	30	30	50	mA	9, 10
NOTES:

1.All data sheet parameters specified to full range of VDD unless otherwise noted. All voltages are referenced to voltage applied to VSS bumps.

2.Supply voltage applied to VDD connections.

3.Supply voltage applied to VDDQ connections.

4.All power supply currents measured with outputs open or deselected.

5.VDD = VDD (max), tKHKH = tKHKH (min), SS registered active, 50% read cycles.

6.VDD = VDD (max), tKHKH = dc, SS registered active.

7.VDD = VDD (max), tKHKH = tKHKH (min), SS registered inactive.

8.VDD = VDD (max), tKHKH = dc, SS registered inactive. ZZ low.

9.VDD = VDD (max), tKHKH = dc, SS registered inactive, ZZ high.

10.200 mV ≥ Vin ≥ VDDQ ± 200 mV.

DC INPUT CHARACTERISTICS

Parameter	Symbol	Min	Max	Unit	Notes
DC Input Logic High	VIH (dc)	1.7	VDD + 0.3	V
DC Input Logic Low	VIL (dc)	± 0.3	0.7	V	1
Input Leakage Current	Ilkg(1)	Ð	± 5	μA	2
Clock Input Leakage Current	Iclkg(1)	Ð	± 8	μA	2
Clock Input Signal Voltage	Vin	± 0.3	VDDQ + 0.3	V
Clock Input Differential Voltage	VDIF (dc)	0.2	VDDQ + 0.6	V	3
Clock Input Common Mode Voltage Range (See Figure 3)	VCM (dc)	1.1	2.1	V	4
NOTES:

1.Inputs may undershoot to ± 0.5 V (peak) for up to 20% tKHKH (e.g., 2 ns at a clock cycle time of 10 ns).

2.0 V ≤ Vin ≤ VDDQ for all pins.

3.Minimum instantaneous differential input voltage required for differential input clock operation.

4.Maximum rejectable common mode input voltage variation.

DC OUTPUT CHARACTERISTICS

Parameter	Symbol	Min	Max	Unit	Notes
Output Leakage Current	Ilkg(0)	±1.0	1.0	μA
Output Low Voltage	VOL	Ð	0.7	V	1
Output High Voltage	VOH	1.7	Ð	V	2

NOTES:

1.IOL = 8.0 mA.

2.IOH = ± 8.0 mA.

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, 0°C ≤ TA ≤ 70°C, Periodically Sampled Rather Than 100% Tested)

	Characteristic	Symbol	Typ	Max	Unit
	Input Capacitance	Cin	4	5	pF
	Input/Output Capacitance	CI/O	7	8	pF
	CK, CK Capacitance	CCK	4	5	pF

MCM69R738A•MCM69R820A	MOTOROLA FAST SRAM
6