Motorola MCM6208CJ20, MCM6208CJ15, MCM6208CJ12, MCM6208CJ12R2, MCM6208CP35 Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document by MCM6208C/D

64K x 4 Fast Static RAM

The MCM6208C is fabricated using Motorola's high±performance silicon±gate CMOS technology. Static design eliminates the need for external clocks or timing strobes, while CMOS circuitry reduces power consumption and provides for greater reliability.

This device meets JEDEC standards for functionality and pinout, and is available in plastic dual±in±line and plastic small±outline J±leaded packages.

•Single 5 V ± 10% Power Supply

•Fully Static Ð No Clock or Timing Strobes Necessary

•Fast Access Times: 12, 15, 20, 25, and 35 ns

•Equal Address and Chip Enable Access Times

•Low Power Operation: 135 ±165 mA Maximum AC

•Fully TTL Compatible Ð Three±State Output

			BLOCK DIAGRAM
	A1
	A2		VCC
	A3		VSS
	A4	ROW	MEMORY ARRAY
	A6		256 ROWS x
		DECODER
			64 x 4 COLUMNS
	A12
	A13
	A14

DQ0				COLUMN I/O
	INPUT
DQ1			COLUMN DECODER
	DATA
DQ2	CONTROL
DQ3	A0	A5	A7	A8	A9	A10	A11	A15

E

W

MCM6208C

P PACKAGE

300 MIL PLASTIC CASE 724A±01

J PACKAGE 300 MIL SOJ CASE 810A±02

PIN ASSIGNMENT

A0			1	24		VCC
A1			2	23		A15
A2			3	22		A14
A3			4	21		A13
A4			5	20		A12
A5			6	19		A11
A6			7	18		A10
A7			8	17		DQ0
A8			9	16		DQ1
A9			10	15		DQ2
			11	14		DQ3
	E
VSS			12	13
						W

PIN NAMES

A0 ± A15 . . . . . . . . . . . . . Address Input

DQ0 ± DQ3 . . . Data Input/Data Output

W . . . . . . . . . . . . . . . . . . . . Write Enable

E . . . . . . . . . . . . . . . . . . . . . . Chip Enable

VCC . . . . . . . . . . . Power Supply (+ 5 V)

VSS . . . . . . . . . . . . . . . . . . . . . . . Ground

NC . . . . . . . . . . . . . . . . . No Connection

REV 4 6/95

Motorola, Inc. 1994

TRUTH TABLE (X = Don't Care)

	E			W		Mode	VCC Current	Output	Cycle
H				X		Not Selected	ISB1, ISB2	High±Z	Ð
	L			H		Read	ICCA	Dout	Read Cycle
	L			L		Write	ICCA	High±Z	Write Cycle

ABSOLUTE MAXIMUM RATINGS (See Note)

Rating	Symbol	Value		Unit
Power Supply Voltage	VCC	± 0.5 to +	7.0	V
Voltage Relative to VSS For Any Pin	Vin, Vout	± 0.5 to VCC + 0.5		V
Except VCC
Output Current	Iout	± 20		mA
Power Dissipation	PD	1.0		W
Temperature Under Bias	Tbias	± 10 to +	85	°C
Operating Temperature	TA	0 to + 70		°C
Storage Temperature Ð Plastic	Tstg	± 55 to + 125		°C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPER-

ATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high±impedance circuit.

This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.

DC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS

Parameter	Symbol	Min	Typ	Max	Unit
Supply Voltage (Operating Voltage Range)	VCC	4.5	5.0	5.5	V
Input High Voltage	VIH	2.2	Ð	VCC + 0.3**	V
Input Low Voltage	VIL	± 0.5*	Ð	0.8	V

*VIL (min) = ± 0.5 V dc; VIL (min) = ± 2.0 V ac (pulse width ≤ 20 ns)

**VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 20 ns)

DC CHARACTERISTICS

				Parameter	Symbol	Min	Max	Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC)					Ilkg(I)	Ð	± 1	μA
Output Leakage Current				= VIH, Vout = 0 to VCC)	Ilkg(O)	Ð	± 1	μA
			(E1
		≥ VCC ± 0.2 V*, Vin ≤ VSS + 0.2 V, or ≥ VCC ± 0.2 V,			ISB2
Standby Current (E						Ð	20	mA
VCC = Max, f = 0 MHz)
Output Low Voltage (IOL = 8.0 mA)					VOL	Ð	0.4	V
Output High Voltage (IOH = ± 4.0 mA)					VOH	2.4	Ð	V

POWER SUPPLY CURRENTS

		Parameter	Symbol	± 12	± 15	± 20	± 25	± 35	Unit
AC Supply Current (Iout = 0 mA, VCC = Max, f = fmax)			ICCA	165	155	145	135	135	mA
		= VIH, VCC = Max, f = fmax)	ISB1
Standby Current (E				55	50	45	40	40	mA

MCM6208C	MOTOROLA FAST SRAM
2

CAPACITANCE (f = 1 MHz, dV = 3 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)

						Characteristic	Symbol	Max	Unit
Address Input Capacitance							Cin	6	pF
Control Pin Input Capacitance							Cin	6	pF
	(E,		G, W)
I/O Capacitance							CI/O	8	pF

AC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level . . . . . . . . . . . .	. . . 1.5	V	Output Timing Measurement Reference Level . . . . . . . . . . . . .		1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	0 to 3.0	V	Output Load . . . . . . . . . . . . . . . .	Figure 1A Unless Otherwise Noted
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 5 ns

READ CYCLE (See Notes 1 and 2)

		± 12		± 15		± 20		± 25			±35
Parameter	Symbol	Min	Max	Min	Max	Min	Max	Min	Max	Min		Max	Unit	Notes
Read Cycle Time	tAVAV	12	Ð	15	Ð	20	Ð	25	Ð	35		Ð	ns	2
Address Access Time	tAVQV	Ð	12	Ð	15	Ð	20	Ð	25	Ð		25	ns
Enable Access Time	tELQV	Ð	12	Ð	15	Ð	20	Ð	25	Ð		25	ns	3
Output Enable Access Time	tGLQV	Ð	6	Ð	8	Ð	10	Ð	12	Ð		Ð	ns
Output Hold from Address Change	tAXQX	4	Ð	4	Ð	4	Ð	4	Ð	4		Ð	ns
Enable Low to Output Active1	tELQX	4	Ð	4	Ð	4	Ð	4	Ð	4		Ð	ns	4, 5, 6
Enable High to Output High±Z	tEHQZ	0	6	0	8	0	9	0	10	0		10	ns	4, 5, 6
Output Enable Low to Output Active	tGLQX	0	Ð	0	Ð	0	Ð	0	Ð	0		Ð	ns	4, 5, 6
Output Enable High to Output High±Z	tGHQZ	0	6	0	7	0	8	0	10	0		Ð	ns	4, 5, 6
Power Up Time	tELICCH	0	Ð	0	Ð	0	Ð	0	Ð	0		Ð	ns
Power Down Time	tEHICCL	Ð	12	Ð	15	Ð	20	Ð	25	Ð		35	ns
NOTES:

1.W is high for read cycle.

2.All timings are referenced from the last valid address to the first transitioning address.

3.Addresses valid prior to or coincident with E going low.

4.At any given voltage and temperature, tEHQZ max is less than tELQX min, and tGHQZ max is less than tGLQX min, both for a given device and from device to device.

5.Transition is measured ± 500 mV from steady±state voltage with load of Figure 1B.

6.This parameter is sampled and not 100% tested.

7.Device is continuously selected (E1 ≤ VIL).

	AC TEST LOADS
			+ 5 V
OUTPUT	RL = 50 Ω		480 Ω
	OUTPUT
Z0	= 50 Ω	Ω	5 pF
	255
	VL = 1.5 V

Figure 1A

Figure 1B

TIMING LIMITS

The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.

MOTOROLA FAST SRAM	MCM6208C
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