MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quint Latch
The MC10H175 is a quint D type latch with common reset and clock lines. This MECL 10KH part is a functional/pinout duplication of the standard MECL 10K family part, with 100% improvement in propagation delay and no increase in power±supply current.
•Propagation Delay, 1.2 ns Typical
•Power Dissipation, 400 mW Typical
•Improved Noise Margin 150 mV (Over Operating Voltage and Temperature Range)
•Voltage Compensated
•MECL 10K±Compatible
MAXIMUM RATINGS
Characteristic |
Symbol |
Rating |
Unit |
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Power Supply (VCC = 0) |
VEE |
±8.0 to 0 |
Vdc |
Input Voltage (VCC = 0) |
VI |
0 to VEE |
Vdc |
Output Current Ð Continuous |
Iout |
50 |
mA |
Ð Surge |
|
100 |
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Operating Temperature Range |
TA |
0 to +75 |
°C |
Storage Temperature Range Ð Plastic |
Tstg |
±55 to +150 |
°C |
Ð Ceramic |
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±55 to +165 |
°C |
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ELECTRICAL CHARACTERISTICS (VEE = ±5.2 V ±5%) (See Note)
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0° |
25° |
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75° |
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Characteristic |
Symbol |
Min |
Max |
Min |
Max |
Min |
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Max |
Unit |
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Power Supply Current |
IE |
Ð |
107 |
Ð |
97 |
Ð |
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107 |
mA |
Input Current High |
IinH |
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μA |
Pins 5,6,7,9,10,12,13 |
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Ð |
565 |
Ð |
335 |
Ð |
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335 |
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Pin 11 |
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Ð |
1120 |
Ð |
660 |
Ð |
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660 |
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Input Current Low |
IinL |
0.5 |
Ð |
0.5 |
Ð |
0.3 |
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Ð |
μA |
High Output Voltage |
VOH |
±1.02 |
±0.84 |
±0.98 |
±0.81 |
±0.92 |
|
±0.735 |
Vdc |
Low Output Voltage |
VOL |
±1.95 |
±1.63 |
±1.95 |
±1.63 |
±1.95 |
|
±1.60 |
Vdc |
High Input Voltage |
VIH |
±1.17 |
±0.84 |
±1.13 |
±0.81 |
±1.07 |
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±0.735 |
Vdc |
Low Input Voltage |
VIL |
±1.95 |
±1.48 |
±1.95 |
±1.48 |
±1.95 |
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±1.45 |
Vdc |
AC PARAMETERS |
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Propagation Delay |
tpd |
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ns |
Data |
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0.6 |
1.6 |
0.6 |
1.6 |
0.6 |
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1.7 |
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Clock |
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0.7 |
1.9 |
0.7 |
2.0 |
0.8 |
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2.1 |
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Reset |
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1.0 |
2.2 |
1.0 |
2.3 |
1.0 |
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2.4 |
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Set±up Time |
tset |
1.5 |
Ð |
1.5 |
Ð |
1.5 |
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Ð |
ns |
Hold Time |
thold |
0.8 |
Ð |
0.8 |
Ð |
0.8 |
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Ð |
ns |
Rise Time |
tr |
0.5 |
1.8 |
0.5 |
1.9 |
0.5 |
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2.0 |
ns |
Fall Time |
tf |
0.5 |
1.8 |
0.5 |
1.9 |
0.5 |
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2.0 |
ns |
NOTE:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50±ohm resistor to ±2.0 volts.
MC10H175
L SUFFIX
CERAMIC PACKAGE
CASE 620±10
P SUFFIX
PLASTIC PACKAGE
CASE 648±08
FN SUFFIX
PLCC
CASE 775±02
TRUTH TABLE
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D |
C0 |
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C1 |
Reset |
Qn+1 |
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L |
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L |
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L |
X |
L |
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H |
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L |
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L |
X |
H |
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X |
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H |
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X |
L |
Qn |
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X |
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X |
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H |
L |
Qn |
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X |
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H |
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X |
H |
L |
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X |
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X |
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H |
H |
L |
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DIP
PIN ASSIGNMENT
VCC1 |
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1 |
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16 |
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VCC2 |
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Q2 |
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2 |
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15 |
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Q1 |
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Q3 |
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3 |
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14 |
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Q0 |
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Q4 |
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4 |
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13 |
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D2 |
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D4 |
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5 |
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12 |
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D1 |
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RESET |
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C0 |
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6 |
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11 |
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D0 |
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C1 |
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7 |
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10 |
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VEE |
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8 |
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9 |
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D3 |
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Pin assignment is for Dual±in±Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 6±11 of the Motorola MECL Data Book (DL122/D).
3/93
Motorola, Inc. 1996 |
2±92 |
REV 5 |
MC10H175
APPLICATION INFORMATION
The MC10H175 is a high speed, low power quint latch. It features five D type latches with common reset and a common two±input clock. Data is transferred on the negative edge of the clock and latched on the positive edge. The two clock inputs are ªORºed together.
Any change on the data input will be reflected at the
outputs while the clock is low. The outputs are latched on the positive transition of the clock. While the clock is in the high state, a change in the information present at the data inputs will not affect the output information. THE RESET
INPUT IS ENABLED ONLY WHEN THE CLOCK IS IN THE HIGH STATE.
LOGIC DIAGRAM
D0 |
10 |
D |
Q |
14 Q0 |
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C |
R |
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D1 |
12 |
D |
Q |
15 Q1 |
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C |
R |
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D2 |
13 |
D |
Q |
2 Q2 |
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C |
R |
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D3 |
9 |
D |
Q |
3 Q3 |
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C |
R |
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D4 |
5 |
D |
Q |
4 Q4 |
C0 |
6 |
C |
R |
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C1 |
7 |
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RESET 11 |
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VCC1 = PIN 1 |
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VCC2 = PIN 16 |
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VEE = PIN 8 |
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MECL Data |
2±93 |
MOTOROLA |
DL122 Ð Rev 6
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