Fairchild Semiconductor 74ACT109SCX, 74ACT109SC, 74ACT109PC, 74ACT109MTCX, 74ACT109MTC Datasheet
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November 1988
Revised August 2000
74AC109 • 74ACT109
Dual JK Positive Edge-Triggered Flip-Flop
General Description
The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes
both Q and Q HIGH
Features
■ICC reduced by 50%
■Outputs source/sink 24 mA
■ACT109 has TTL-compatible inputs
Ordering Code:
Order Number |
Package Number |
Package Description |
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74AC109SC |
M16A |
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow |
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74AC109SJ |
M16D |
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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74AC109MTC |
MTC16 |
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide |
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74AC109PC |
N16E |
16-Lead Plastic Dual-in-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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74ACT109SC |
M16A |
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow |
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74AC109MTC |
MTC16 |
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide |
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74ACT109PC |
N16E |
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide |
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Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram |
Pin Descriptions |
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Pin Names |
Description |
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J1, J2, |
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1, |
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2 |
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Data Inputs |
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K |
K |
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CP1, CP2 |
Clock Pulse Inputs |
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D2 |
Direct Clear Inputs |
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C |
D1, |
C |
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D2 |
Direct Set Inputs |
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S |
D1, |
S |
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Q1, Q2, |
Q |
1, |
Q |
2 |
Outputs |
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FACT is a trademark of Fairchild Semiconductor Corporation.
Flop-Flip Triggered-Edge Positive JK Dual 74ACT109 • 74AC109
© 2000 Fairchild Semiconductor Corporation |
DS009923 |
www.fairchildsemi.com |
74AC109 • 74ACT109
Logic Symbols
IEEE/IEC
Truth Table
(each half)
H = |
HIGH Voltage Level |
L = |
LOW Voltage Level |
= |
LOW-to-HIGH Transition |
X = |
Immaterial |
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Inputs |
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Outputs |
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SD |
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CD |
CP |
J |
K |
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Q |
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Q |
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L |
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H |
X |
X |
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X |
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H |
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L |
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H |
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L |
X |
X |
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X |
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L |
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H |
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L |
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L |
X |
X |
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X |
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H |
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H |
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H |
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H |
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L |
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L |
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L |
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H |
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H |
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H |
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H |
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L |
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Toggle |
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H |
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H |
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L |
H |
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Q0 |
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Q |
0 |
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H |
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H |
H |
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H |
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L |
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H |
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H |
L |
X |
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X |
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Q0 |
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Q |
0 |
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Q0(Q0) = Previous Q0(Q0) before LOW-to-HIGH Transition of Clock
Logic Diagram (one half shown)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) |
− 0.5V to + 7.0V |
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DC Input Diode Current (IIK) |
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VI = |
− 0.5V |
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− 20 mA |
VI = |
VCC + 0.5V |
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+ 20 mA |
DC Input Voltage (VI) |
− 0.5V to VCC + 0.5V |
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DC Output Diode Current (IOK) |
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VO = |
− 0.5V |
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− 20 mA |
VO = |
VCC + 0.5V |
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+ 20 mA |
DC Output Voltage (VO) |
− 0.5V to VCC + 0.5V |
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DC Output Source |
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or Sink Current (IO) |
± |
50 mA |
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DC VCC or Ground Current |
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per Output Pin (ICC or IGND) |
± |
50 mA |
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Storage Temperature (TSTG) |
− 65° C to + 150° C |
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Junction Temperature (TJ) |
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PDIP |
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140° C |
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Recommended Operating
Conditions
Supply Voltage (VCC) |
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AC |
2.0V to 6.0V |
ACT |
4.5V to 5.5V |
Input Voltage (VI) |
0V to VCC |
Output Voltage (VO) |
0V to VCC |
Operating Temperature (TA) |
− 40° C to + 85° C |
Minimum Input Edge Rate (∆ V/∆ t) |
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AC Devices |
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VIN from 30% to 70% of VCC |
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VCC @ 3.3V, 4.5V, 5.5V |
125 mV/ns |
Minimum Input Edge Rate (∆ V/∆ t) |
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ACT Devices |
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VIN from 0.8V to 2.0V |
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VCC @ 4.5V, 5.5V |
125 mV/ns |
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables.Fairchild does not recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics for AC
Symbol |
Parameter |
VCC |
TA = + 25° C |
TA = − 40° C to + 85° C |
Units |
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Conditions |
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(V) |
Typ |
Guaranteed Limits |
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VIH |
Minimum HIGH Level |
3.0 |
1.5 |
2.1 |
2.1 |
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VOUT = |
0.1V |
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Input Voltage |
4.5 |
2.25 |
3.15 |
3.15 |
V |
or VCC − |
0.1V |
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5.5 |
2.75 |
3.85 |
3.85 |
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VIL |
Maximum LOW Level |
3.0 |
1.5 |
0.9 |
0.9 |
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VOUT = |
0.1V |
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Input Voltage |
4.5 |
2.25 |
1.35 |
1.35 |
V |
or VCC − |
0.1V |
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5.5 |
2.75 |
1.65 |
1.65 |
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VOH |
Minimum HIGH Level |
3.0 |
2.99 |
2.9 |
2.9 |
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Output Voltage |
4.5 |
4.49 |
4.4 |
4.4 |
V |
IOUT = |
− |
50 µ A |
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5.5 |
5.49 |
5.4 |
5.4 |
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VIN = |
VIL or VIH |
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3.0 |
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2.56 |
2.46 |
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IOH = |
− |
12 mA |
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4.5 |
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3.86 |
3.76 |
V |
IOH = |
− |
24 mA |
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5.5 |
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4.86 |
4.76 |
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IOH = |
− 24 mA (Note 2) |
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VOL |
Maximum LOW Level |
3.0 |
0.002 |
0.1 |
0.1 |
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Output Voltage |
4.5 |
0.001 |
0.1 |
0.1 |
V |
IOUT = |
50 µ A |
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5.5 |
0.001 |
0.1 |
0.1 |
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VIN = |
VIL or VIH |
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3.0 |
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0.36 |
0.44 |
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IOL = |
12 mA |
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4.5 |
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0.36 |
0.44 |
V |
IOL = |
24 mA |
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5.5 |
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0.36 |
0.44 |
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IOL = |
24 mA (Note 2) |
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IIN |
Maximum Input |
5.5 |
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± 0.1 |
± 1.0 |
µ A |
VI = |
VCC, |
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(Note 4) |
Leakage Current |
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GND |
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IOLD |
Minimum Dynamic |
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5.5 |
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75 |
mA |
VOLD = |
1.65V Max |
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IOHD |
Output Current (Note 3) |
5.5 |
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− 75 |
mA |
VOHD = |
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3.85V Min |
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ICC |
Maximum Quiescent |
5.5 |
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2.0 |
20.0 |
µ A |
VIN = |
VCC |
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(Note 4) |
Supply Current |
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or GND |
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Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
74ACT109 • 74AC109
3 |
www.fairchildsemi.com |
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