June 1988
Revised November 1999
74AC399 • 74ACT399 Quad 2-Port Register
General Description
The AC/ACT399 is the logical equivalent of a quad 2-input multiplexer feeding into four edge-triggered flip-flops. A common Select input determines which of the two 4-bit words is accepted. The selected data enters the flip-flop on the rising edge of the clock.
Features
■ICC reduced by 50%
■Select inputs from two data sources
■Fully positive edge-triggered operation
■Outputs source/sink 24 mA
■AC/ACT399 has TTL-compatible inputs
Ordering Code:
Order Number |
Package Number |
Package Description |
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74AC399SC |
M16A |
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body |
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74AC399PC |
N16E |
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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74ACT399SC |
M16A |
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body |
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74ACT399SJ |
M16D |
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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74ACT399PC |
N16E |
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols |
Connection Diagram |
IEEE/IEC
Pin Descriptions
Pin Names |
Description |
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S |
Common Select Input |
CP |
Clock Pulse Input |
I0a–I0d |
Data Inputs from Source 0 |
I1a–I1d |
Data Inputs from Source 1 |
Qa–Qd |
Register True Outputs |
FACT is a trademark of Fairchild Semiconductor Corporation.
Register Port-2 Quad 74ACT399 • 74AC399
© 1999 Fairchild Semiconductor Corporation |
DS009789 |
www.fairchildsemi.com |
74AC399 • 74ACT399
Functional Description
The AC/ACT399 is a high-speed quad 2-port register. It selects four bits of data from either of two sources (Ports) under control of a common Select input (S). The selected data is transferred to a 4-bit output register synchronous with the LOW-to-HIGH transition of the Clock input (CP). The 4-bit D-type output register is fully edge-triggered. The Data inputs (I0x, I1x) and Select input (S) must be stable only a setup time prior to and hold time after the LOW-to- HIGH transition of the Clock input for predictable operation.
Logic Diagram
Function Table
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Inputs |
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Outputs |
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S |
I0 |
I1 |
CP |
Q |
Q |
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L |
L |
X |
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L |
H |
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L |
H |
X |
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H |
L |
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H |
X |
L |
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L |
H |
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H |
X |
H |
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H |
L |
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H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) |
− 0.5V to + 7.0V |
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DC Input Diode Current (IIK) |
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VI = |
− 0.5V |
− 20 mA |
VI = |
VCC + 0.5V |
+ 20 mA |
DC Input Voltage (VI) |
− 0.5V to VCC + 0.5V |
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DC Output Diode Current (IOK) |
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VO = |
− 0.5V |
− 20 mA |
VO = |
VCC + 0.5V |
+ 20 mA |
DC Output Voltage (VO) |
− 0.5V to VCC + 0.5V |
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DC Output Source or |
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Sink Current (IO) |
± 50 mA |
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DC VCC or Ground Current |
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per Output Pin (ICC or IGND) |
± 50 mA |
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Storage Temperature (TSTG) |
− 65° C to + 150° C |
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Junction Temperature (TJ) |
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PDIP |
+ 140° C |
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Recommended Operating
Conditions
Supply Voltage (VCC) |
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AC |
2.0V to 6.0V |
ACT |
4.5V to 5.5V |
Input Voltage (VI) |
0V to VCC |
Output Voltage (VO) |
0V to VCC |
Operating Temperature (TA) |
− 40° C to + 85° C |
Minimum Input Edge Rate (∆ V/∆ t) |
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AC Devices |
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VIN from 30% to 70% of VCC |
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VCC @ 3.3V, 4.5V, 5.5V |
125 mV/ns |
Minimum Input Edge Rate (∆ V/∆ t) |
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ACT Devices |
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VIN from 0.8V to 2.0V |
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VCC @ 4.5V, 5.5V |
125 mV/ns |
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics for AC
Symbol |
Parameter |
VCC |
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TA = + 25° C |
TA = − 40° C to + 85° C |
Units |
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Conditions |
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(V) |
Typ |
Guaranteed Limits |
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VIH |
Minimum HIGH Level |
3.0 |
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1.5 |
2.1 |
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2.1 |
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VOUT = |
0.1V |
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Input Voltage |
4.5 |
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2.25 |
3.15 |
3.15 |
V |
or VCC − 0.1V |
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5.5 |
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2.75 |
3.85 |
3.85 |
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VIL |
Maximum LOW Level |
3.0 |
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1.5 |
0.9 |
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0.9 |
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VOUT = |
0.1V |
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Input Voltage |
4.5 |
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2.25 |
1.35 |
1.35 |
V |
or VCC − |
0.1V |
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5.5 |
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2.75 |
1.65 |
1.65 |
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VOH |
Minimum HIGH Level |
3.0 |
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2.99 |
2.9 |
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2.9 |
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Output Voltage |
4.5 |
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4.49 |
4.4 |
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4.4 |
V |
IOUT = |
− |
50 µ A |
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5.5 |
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5.49 |
5.4 |
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5.4 |
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VIN = |
VIL or VIH |
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3.0 |
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2.56 |
2.46 |
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IOH= − 12 mA |
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4.5 |
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3.86 |
3.76 |
V |
IOH= − 24 mA |
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5.5 |
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4.86 |
4.76 |
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IOH= − 24 mA (Note 2) |
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VOL |
Maximum LOW Level |
3.0 |
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0.002 |
0.1 |
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0.1 |
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Output Voltage |
4.5 |
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0.001 |
0.1 |
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0.1 |
V |
IOUT = |
50 µ A |
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5.5 |
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0.001 |
0.1 |
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0.1 |
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VIN = |
VIL or VIH |
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3.0 |
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0.36 |
0.44 |
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IOL= 12 mA |
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4.5 |
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0.36 |
0.44 |
V |
IOL = 24 mA |
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5.5 |
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0.36 |
0.44 |
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IOL = 24 mA (Note 2) |
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IIN |
Maximum Input Leakage Current |
5.5 |
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± 0.1 |
± |
1.0 |
µ A |
VI = |
VCC, GND |
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IOZ |
Maximum 3-STATE |
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VI (OE) = VIL, VIH |
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Current |
5.5 |
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± 0.5 |
± |
5.0 |
µ A |
VI = |
VCC, GND |
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VO = |
VCC, GND |
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IOLD |
Minimum Dynamic |
5.5 |
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75 |
mA |
VOLD = |
1.65V Max |
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IOHD |
Output Current (Note 3) |
5.5 |
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− 75 |
mA |
VOHD = |
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3.85V Min |
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ICC |
Maximum Quiescent Supply Current |
5.5 |
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4.0 |
40.0 |
µ A |
VIN = |
VCC or GND |
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Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
74ACT399 • 74AC399
3 |
www.fairchildsemi.com |
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