Texas Instruments TIBPAL22VP10-25MJTB, TIBPAL22VP10-25MWB, TIBPAL22VP10-25MFKB, TIBPAL22VP10-20CNT, TIBPAL22VP10-20CFN Datasheet

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TIBPAL22VP10-20C, TIBPAL22VP10-25M

HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS013 – D2943, FEBRUARY 1987 – REVISED JUNE 1991

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

• Functionally Equivalent to the

TIBPAL22V10/10A, with Additional

Feedback Paths in the Output Logic

Macrocell

• Choice of Operating Speeds:

TIBPAL22VP10-20C . . . 20 ns Max

TIBPAL22VP10-25M . . . 25 ns Max

• Variable Product Term Distribution

Allows More Complex Functions to Be

Implemented

• Each Output Is User Programmable for

Registered or Combinational Operation,

Polarity, and Output Enable Control

• TTL-Level Preload for Improved Testability

• Extra Terms Provide Logical Synchronous

Set and Asynchronous Reset Capability

• Fast Programming, High Programming

Yield, and Unsurpassed Reliability Ensured

Using Ti-W Fuses

• AC and DC Testing Done at the Factory

Utilizing Special Designed-In Test Features

• Dependable Texas Instruments Quality and

Reliability

• Package Options Include Plastic

Dual-In-Line and Chip Carrier Packages

description

The TIBPAL22VP10’ is equivalent to the

TIBPAL22V10A but offers additional flexibility in

the output structure. The improved output

macrocell uses the registered outputs as inputs

when in a high-impedance condition. This

provides two additional output configurations for a

total of six possible macrocell configurations all of

which are shown in Figure 1.

These devices contain up to 22 inputs and 10 outputs. They incorporate the unique capability of defining and

programming the architecture of each output on an individual basis. Outputs may be registered or nonregistered

and inverting or noninverting. In addition, the data may be fed back into the array from either the register or the

I/O port. The ten potential outputs are enabled through the use of individual product terms.

Further advantages can be seen in the introduction of variable product term distribution. This technique

allocates from 8 to 16 logical product terms to each output for an average of 12 product terms per output. This

variable allocation of terms allows far more complex functions to be implemented than in previously available

devices.

These devices are covered by U.S. Patent 4,410,987.

IMPACT-X is a trademark of Texas Instruments Incorporated.

CLK/I

GND

I/O/Q

3212827

12 13

I/O/Q

426

14 15 16 1718

GND

I/O/Q

CLK/I

I/O/Q

NC – No internal connection

Pin assignments in operating mode

C SUFFIX . . . NT PACKAGE

M SUFFIX . . . JT PACKAGE

(TOP VIEW)

C SUFFIX . . . FN PACKAGE

M SUFFIX . . . FK PACKAGE

(TOP VIEW)

TIBPAL22VP10-20C, TIBPAL22VP10-25M

HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS013 – D2943, FEBRUARY 1987 – REVISED JUNE 1991

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

Circuit design is enhanced by the addition of a synchronous set and an asynchronous reset product term. These

functions are common to all registers. When the synchronous set product term is a logic 1, the output registers

are loaded with a logic 1 on the next low-to-high clock transition. When the asynchronous reset product term

is a logic 1, the output registers are loaded with a logic 0. The output logic level after set or reset depends on

the polarity selected during programming. Output registers can be preloaded to any desired state during testing.

Preloading permits full logical verification during product testing.

With features such as programmable output logic macrocells and variable product term distribution, the

TIBP AL22VP10’ of fers quick design and development of custom LSI functions with complexities of 500 to 800

equivalent gates. Since each of the ten output pins may be individually configured as inputs on either a

temporary or permanent basis, functions requiring up to 21 inputs and a single output or down to 12 inputs and

10 outputs are possible.

A power-up clear function is supplied that forces all registered outputs to a predetermined state after power is

applied to the device. Registered outputs selected as active-low power-up with their outputs high. Registered

outputs selected as active-high power-up with their outputs low.

A single security fuse is provided on each device to discourage unauthorized copying of fuse patterns. Once

blown, the verification circuitry is disabled and all other fuses will appear to be open.

The TIBPAL22V10-20C is characterized for operation from 0°C to 75°C. The TIBPAL22V10-25M is

characterized for operation over the full military temperature range of –55°C to 125°C.

TIBPAL22VP10-20C, TIBPAL22VP10-25M

HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS013 – D2943, FEBRUARY 1987 – REVISED JUNE 1991

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram (positive logic)

I/O/Q

44 x 132

I/O/Q

CLK/I

Set

Reset

Output

Logic

Macrocell

denotes fused inputs

TIBPAL22VP10-20C, TIBPAL22VP10-25M

HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS013 – D2943, FEBRUARY 1987 – REVISED JUNE 1991

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0 4 8 1216202428

Increments

First

Fuse

Numbers

32 36 40

Macro-

cell

R = 5809

P = 5808

R = 5811

P = 5810

R = 5813

P = 5812

R = 5815

P = 5814

R = 5817

P = 5816

logic symbol (positive logic)

Asynchronous Reset

(to all registers)

396

440

880

924

1452

1496

2112

2156

2860

I/O/Q

CLK/I

Macro-

cell

Macro-

cell

Macro-

cell

Macro-

cell

TIBPAL22VP10-20C, TIBPAL22VP10-25M

HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS013 – D2943, FEBRUARY 1987 – REVISED JUNE 1991

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Fuse number = First fuse number + Increment

R = 5819

P = 5818

R = 5821

P = 5820

R = 5823

P = 5822

R = 5825

P = 5824

R = 5827

P = 5826

Synchronous Set

(to all registers)

Inside each MACROCELL the ”P” fuse is the polarity fuse and the ”R” fuse is the register fuse.

2904

3608

3652

4268

4312

4840

4884

5324

5368

5720

5764

I/O/Q

Macro-

cell

Macro-

cell

Macro-

cell

Macro-

cell

Macro-

cell

TIBPAL22VP10-20C, TIBPAL22VP10-25M

HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS013 – D2943, FEBRUARY 1987 – REVISED JUNE 1991

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

output logic macrocell diagram

MUX

I = 0

MUX

1/2/3

From Clock Buffer

AR = asynchronous reset

SS = synchronous set

Output Logic Macrocell

†

This fuse is unique to the Texas Instruments TIBPAL22VP10’. It allows feedback from the I/O port using registered outputs as shown in the

macrocell fusing logic function table.

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