Texas Instruments TIBPAL20L8-15CFN, TIBPAL20R6-15CFN, TIBPAL20R6-15CNT Datasheet

TIBPAL20L8-15C, TIBPAL20R4-15C, TIBPAL20R6-15C, TIBPAL20R8-15C TIBPAL20L8-20M, TIBPAL20R4-20M, TIBPAL20R6-20M, TIBPAL20R8-20M HIGH-PERFORMANCE IMPACT PAL CIRCUITS

SRPS021 ± D2920, JUNE 1986 ± REVISED AUGUST 1989

• High-Performance: fmax (w/o feedback)

TIBPAL20L8'

C SUFFIX . . . JT OR NT PACKAGE

TIBPAL20R' -15C Series . . . 45 MHz

M SUFFIX . . . JT OR W PACKAGE

TIBPAL20R' -20M Series . . . 41.6 MHz

(TOP VIEW)

• High-Performance . . . 45 MHz Min

I

1

24

VCC

• Reduced ICC of 180 mA Max

I

2

23

I

• Functionally Equivalent, but Faster Than

I

3

22

O

PAL20L8, PAL20R4, PAL20R6, PAL20R8

I

4

21

I/O

I

5

20

I/O

• Power-Up Clear on Registered Devices (All

I

6

19

I/O

Register Outputs are Set Low, but Voltage

I

7

18

I/O

Levels at the Output Pins Go High)

I

8

17

I/O

• Preload Capability on Output Registers

I

9

16

I/O

Simplifies Testing

I

10

15

O

I

11

14

I

• Package Options Include Both Plastic and

GND

12

13

I

Ceramic Chip Carriers in Addition to Plastic

and Ceramic DIPs

TIBPAL20L8'

I

3-STATE

REGISTERED

I/O

C SUFFIX . . . FN PACKAGE

DEVICE

PORT

M SUFFIX . . . FK PACKAGE

INPUTS

O OUTPUTS

Q OUTPUTS

S

PAL20L8

14

2

0

6

(TOP VIEW)

PAL20R4

12

0

4 (3-state buffers)

4

I I I NC

CC

PAL20R6

12

0

6 (3-state buffers)

2

V

I O

PAL20R8

12

0

8 (3-state buffers)

0

4

3

2

1

28

27 26

description

I

5

25

I/O

I

6

24

I/O

These programmable array logic devices feature

I

7

23

I/O

NC

8

22

NC

high speed

and

functional

equivalency when

I

9

21

I/O

compared with currently available devices. These

I

10

20

I/O

IMPACT circuits combine the latest Advanced

11

Low-Power

Schottky technology with

proven

I

19

I/O

12 13 14

titanium-tungsten

fuses

to

provide

reliable,

15 16 17 18

high-performance substitutes for conventional

I

I

GND

NC

I

I O

TTL logic. Their easy programmability allows for

quick design of custom functions and typically

NC ± No internal connection

results in a more compact circuit board. In

Pin assignments in operating mode

addition, chip carriers are available for futher

reduction in board space.

Extra circuitry has been provided to allow loading of each register asynchronously to either a high or low state. This feature simplifies testing because the registers can be set to an initial state prior to executing the test sequence.

The TIBPAL20' C series is characterized from 0°C to 75°C. The TIBPAL20' M series is characterized for operation over the full military temperature range of ±55°C to 125°C.

These devices are covered by U.S. Patent 4,410,987.

IMPACT is a trademark of Texas Instruments Incorporated.

PAL is a registered trademark of Advanced Micro Devices Inc.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1989, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

1

TIBPAL20R4-15C, TIBPAL20R6-15C, TIBPAL20R8-15C

TIBPAL20R4-20M, TIBPAL20R6-20M, TIBPAL20R8-20M

HIGH-PERFORMANCE IMPACT PAL CIRCUITS

SRPS021 ± D2920, JUNE 1986 ± REVISED AUGUST 1989

TIBPAL20R4'						TIBPAL20R4'
C SUFFIX . . . JT OR NT PACKAGE					C SUFFIX . . . FN PACKAGE
M SUFFIX . . . JT OR W PACKAGE					M SUFFIX . . . FK PACKAGE
	(TOP VIEW)					(TOP VIEW)
CLK	1	24	VCC				CLK	NC	CC	I/O
					I	I			V I
I	2	23	I		4	3	2	1	28 27 26
I	3	22	I/O	I							I/O
I	4	21	I/O		5					25
				I	6					24	Q
I	5	20	Q
I	6	19	Q	I	7					23	Q
I	7	18	Q	NC	8					22	NC
I	8	17	Q	I	9					21	Q
I	9	16	I/O	I	10					20	Q
I	10	15	I/O
				I	11					19	I/O
I	11	14	I
					12 13 14 15 16 17 18
GND	12	13	OE		I	I	GND	NC	OE I	I/O
TIBPAL20R6'						TIBPAL20R6'
C SUFFIX . . . JT OR NT PACKAGE					C SUFFIX . . . FN PACKAGE
M SUFFIX . . . JT OR W PACKAGE					M SUFFIX . . . FK PACKAGE
	(TOP VIEW)					(TOP VIEW)
CLK	1	24	VCC				CLK	NC	CC	I/O
					I	I			V I
I	2	23	I		4	3	2	1	28 27 26
I	3	22	I/O	I							Q
I	4	21	Q		5					25
				I	6					24	Q
I	5	20	Q
I	6	19	Q	I	7					23	Q
I	7	18	Q	NC	8					22	NC
I	8	17	Q	I	9					21	Q
I	9	16	Q	I	10					20	Q
I	10	15	I/O
				I	11					19	Q
I	11	14	I
					12 13 14 15 16 17 18
GND	12	13	OE		I	I	GND	NC	OE I	I/O
TIBPAL20R8'						TIBPAL20R8'
C SUFFIX . . . JT OR NT PACKAGE					C SUFFIX . . . FN PACKAGE
M SUFFIX . . . JT OR W PACKAGE					M SUFFIX . . . FK PACKAGE
	(TOP VIEW)					(TOP VIEW)
CLK	1	24	VCC				CLK	NC	CC	Q
					I	I			V I
I	2	23	I		4	3	2	1	28 27 26
I	3	22	Q	I							Q
I	4	21	Q		5					25
				I	6					24	Q
I	5	20	Q
I	6	19	Q	I	7					23	Q
I	7	18	Q	NC	8					22	NC
I	8	17	Q	I	9					21	Q
I	9	16	Q	I	10					20	Q
I	10	15	Q
				I	11					19	Q
I	11	14	I
					12 13 14 15 16 17 18
GND	12	13	OE		I	I	GND	NC	OE I	Q
Pin assignments in operating mode				NC ± No internal connection

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TIBPAL20L8-15C, TIBPAL20R4-15C

TIBPAL20L8-20M, TIBPAL20R4-20M

HIGH-PERFORMANCE IMPACT PAL CIRCUITS

SRPS021 ± D2920, JUNE 1986 ± REVISED AUGUST 1989

functional block diagrams (positive logic)

TIBPAL20L8'

	20 x
14	20
I
6	20

OE

CLK

	20 x
12	20
I
4
4	20

&	EN ≥ 1
40 X 64 7	O
7	O
7	I/O
7	I/O
7	I/O
7	I/O
7	I/O
7	I/O
6

TIBPAL20R4'
			EN 2
			C1
&	8	≥ 1	I = 0 2
40 X 64			1D
	8

8

8

EN ≥ 1

7

7

7

7

4

4

Q

Q

Q

Q

I/O

I/O

I/O

I/O

denotes fused inputs

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

3

TIBPAL20R6-15C, TIBPAL20R8-15C

TIBPAL20R6-20M, TIBPAL20R8-20M HIGH-PERFORMANCE IMPACT PAL CIRCUITS

SRPS021 ± D2920, JUNE 1986 ± REVISED AUGUST 1989

functional block diagrams (positive logic)

TIBPAL20R6'

OE				EN 2
CLK				C1
	&	8	≥ 1	I = 0 2
	40 X 64			1D
		8
	20 x	8
12	20
I		8
6
		8
2	20
		8
		7	EN ≥ 1
		7
		2
			6

		TIBPAL20R8'
OE				EN 2
CLK				C1
	&	8	≥ 1	I = 0 2
	40 X 64			1D
		8
	20 x	8
12	20
I		8
		8
8	20
		8

8

8

8

denotes fused inputs

Q

Q

Q

Q

Q

Q

I/O

I/O

Q

Q

Q

Q

Q

Q

Q

Q

4	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TIBPAL20L8-15C

TIBPAL20L8-20M

HIGH-PERFORMANCE IMPACT PAL CIRCUITS

SRPS021 ± D2920, JUNE 1986 ± REVISED AUGUST 1989

logic diagram (positive logic)

1
I						Increment
	0	4	8	12	16	20	24	28	32	36	39
2											23
I											I
First Fuse
Numbers
	0
	40
	80										22
	120
	160										O
	200
	240
3	280
I

	320
	360
	400	21
	440
	480	I/O
	520
	560
4	600
I
	640
	680
	720	20
	760
	800	I/O
	840
	880
5	920
I
	960
	1000
	1040	19
	1080
	1120	I/O
	1160
	1200
6	1240
I
	1280
	1320
	1360	18
	1400
	1440	I/O
	1480
	1520
7	1560
I
	1600
	1640
	1680	17
	1720
	1760	I/O
	1800
	1840
8	1880
I
	1920
	1960
	2000	16
	2040
	2080	I/O
	2120
	2160
9	2200
I
	2240
	2280
	2320	15
	2360
	2400	O
	2440
	2480
10 2520		14
I		I
11		13
I		I

Fuse number = First fuse number + Increment

Pin numbers shown are for JT, NT, and W packages.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

5

TIBPAL20R4-15C

TIBPAL20R4-20M

HIGH-PERFORMANCE IMPACT PAL CIRCUITS

SRPS021 ± D2920, JUNE 1986 ± REVISED AUGUST 1989

logic diagram (positive logic)

1

CLK

Increment

0

4

8

12

16

20

24

28

32

36

39

2

I

First Fuse

Numbers

0

40

80

120

160

200

240

3 280

I

320

360

400

440

480

520

560

4 600

I

640

680

720

760

800

840

880

5 920

I

960

1000

1040

1080

1120

1160

1200

6 1240

I

1280

1320

1360

1400

1440

1480

1520

7 1560

I

1600

1640

1680

1720

1760

1800

1840

8 1880

I

1920

1960

2000

2040

2080

2120

2160

9 2200

I

2240

2280

2320

2360

2400

2440

2480

10 2520

I

11

I

Fuse number = First fuse number + Increment

Pin numbers shown are for JT, NT, and W packages.

23

I

22

I/O

21

I/O

	I = 0	20
	1D
		Q
	C1
	I = 0	19
	1D
		Q
	C1
	I = 0	18
	1D
		Q
	C1
	I = 0	17
	1D
		Q
	C1

16

I/O

15

I/O

14

I

13

OE

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