Texas Instruments TIBPAL20R8-5CNT, TIBPAL20R8-5CFN, TIBPAL20R8-7MWB, TIBPAL20R8-7MJTB, TIBPAL20R4-5CNT Datasheet

TIBPAL20L8-5C, TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C

TIBPAL20L8-7M, TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M

HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS

		SRPS010F ± D3353, OCTOBER 1989 ± REVISED SEPTEMBER 1992
	• High-Performance Operation:		TIBPAL20L8'
		C SUFFIX . . . JT OR NT PACKAGE
	fmax (no feedback)
		M SUFFIX . . . JT PACKAGE
	TIBPAL20R' -5C Series . . . 125 MHz Min			(TOP VIEW)
	TIBPAL20R' -7M Series . . . 100 MHz Min
	fmax (internal feedback)	I		1	24			VCC
	TIBPAL20R' -5C Series . . . 125 MHz Min	I		2	23			I
	TIBPAL20R' -7M Series . . . 100 MHz Min	I		3	22			O
	fmax (external feedback)
		I		4	21			I/O
	TIBPAL20R' -5C Series . . . 117 MHz Min	I		5	20			I/O
	TIBPAL20R' -7M Series . . . 74 MHz Min
		I		6	19			I/O
	Propagation Delay
		I		7	18			I/O
	TIBPAL20L8-5C Series . . . 5 ns Max
		I		8	17			I/O
	TIBPAL20L8-7M Series . . . 7 ns Max
		I		9	16			I/O
	TIBPAL20R' -5C Series
		I		10	15			O
	(CLK-to-Q) . . . 4 ns Max
		I		11	14			I
	TIBPAL20R' -7M Series
		GND		12	13			I
	(CLK-to-Q) . . . 6.5 ns Max

•Functionally Equivalent, but Faster Than, Existing 24-Pin PLDs

•Preload Capability on Output Registers Simplifies Testing

•Power-Up Clear on Registered Devices (All Register Outputs are Set Low, but Voltage Levels at the Output Pins Go High)

•Package Options Include Both Plastic and Ceramic Chip Carriers in Addition to Plastic and Ceramic DIPs

•Security Fuse Prevents Duplication

		I	3-STATE	REGISTERED	I/O
	DEVICE				PORT
		INPUTS	O OUTPUTS	Q OUTPUTS
					S
	PAL20L8	14	2	0	6
	PAL20R4	12	0	4 (3-state buffers)	4
	PAL20R6	12	0	6 (3-state buffers)	2
	PAL20R8	12	0	8 (3-state buffers)	0

description

TIBPAL20L8'

C SUFFIX . . . FN PACKAGE

M SUFFIX . . . FK PACKAGE

(TOP VIEW)

	I I I NC				CC	O
					V I
	4	3	2	1	28 27 26
I	5					25	I/O
I	6					24	I/O
I	7					23	I/O
NC	8					22	NC
I	9					21	I/O
I	10					20	I/O
I	11					19	I/O
	12 13 14			15 16 17 18
	I	I	GND	NC	I I	O

NC ± No internal connection

Pin assignments in operating mode

These programmable array logic devices feature high speed and functional equivalency when compared with currently available devices. These IMPACT-X circuits combine the latest Advanced Low-Power Schottky technology with proven titanium-tungsten fuses to provide reliable, high-performance substitutes for conventional TTL logic. Their easy programmability allows for quick design of custom functions and typically results in a more compact circuit board.

The TIBPAL20' C series is characterized from 0°C to 75°C. The TIBPAL20' M series is characterized for operation over the full military temperature range of ±55°C to 125°C.

These devices are covered by U.S. Patent 4,410,987.

IMPACT-X is a trademark of Texas Instruments Incorporated.

PAL is a registered trademark of Advanced Micro Devices Inc.

This document contains information on products in more than one	Copyright 1992, Texas Instruments Incorporated
phase of development. The status of each device is indicated on the
page(s) specifying its electrical characteristics.
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265	1

TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C

TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M

HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS

SRPS010F ± D3353, OCTOBER 1989 ± REVISED SEPTEMBER 1992

TIBPAL20R4'						TIBPAL20R4'
C SUFFIX . . . JT OR NT PACKAGE					C SUFFIX . . . FN PACKAGE
M SUFFIX . . . JT PACKAGE					M SUFFIX . . . FK PACKAGE
	(TOP VIEW)					(TOP VIEW)
CLK	1	24	VCC				CLK	NC	CC	I/O
					I	I			V I
I	2	23	I		4	3	2	1	28 27 26
I	3	22	I/O	I							I/O
I	4	21	I/O		5					25
				I	6					24	Q
I	5	20	Q
I	6	19	Q	I	7					23	Q
I	7	18	Q	NC	8					22	NC
I	8	17	Q	I	9					21	Q
I	9	16	I/O	I	10					20	Q
I	10	15	I/O
				I	11					19	I/O
I	11	14	I
					12 13 14 15 16 17 18
GND	12	13	OE		I	I	GND	NC	OE I	I/O
TIBPAL20R6'						TIBPAL20R6'
C SUFFIX . . . JT OR NT PACKAGE					C SUFFIX . . . FN PACKAGE
M SUFFIX . . . JT PACKAGE					M SUFFIX . . . FK PACKAGE
	(TOP VIEW)					(TOP VIEW)
CLK	1	24	VCC				CLK	NC	CC	I/O
					I	I			V I
I	2	23	I		4	3	2	1	28 27 26
I	3	22	I/O	I							Q
I	4	21	Q		5					25
				I	6					24	Q
I	5	20	Q
I	6	19	Q	I	7					23	Q
I	7	18	Q	NC	8					22	NC
I	8	17	Q	I	9					21	Q
I	9	16	Q	I	10					20	Q
I	10	15	I/O
				I	11					19	Q
I	11	14	I
					12 13 14 15 16 17 18
GND	12	13	OE		I	I	GND	NC	OE I	I/O
TIBPAL20R8'						TIBPAL20R8'
C SUFFIX . . . JT OR NT PACKAGE					C SUFFIX . . . FN PACKAGE
M SUFFIX . . . JT PACKAGE					M SUFFIX . . . FK PACKAGE
	(TOP VIEW)					(TOP VIEW)
CLK	1	24	VCC				CLK	NC	CC	Q
					I	I			V I
I	2	23	I		4	3	2	1	28 27 26
I	3	22	Q	I							Q
I	4	21	Q		5					25
				I	6					24	Q
I	5	20	Q
I	6	19	Q	I	7					23	Q
I	7	18	Q	NC	8					22	NC
I	8	17	Q	I	9					21	Q
I	9	16	Q	I	10					20	Q
I	10	15	Q
				I	11					19	Q
I	11	14	I
					12 13 14 15 16 17 18
GND	12	13	OE		I	I	GND	NC	OE I	Q
Pin assignments in operating mode				NC ± No internal connection

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TIBPAL20L8-5C, TIBPAL20R4-5C

TIBPAL20L8-7M, TIBPAL20R4-7M HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS

SRPS010F ± D3353, OCTOBER 1989 ± REVISED SEPTEMBER 1992

functional block diagrams (positive logic)

TIBPAL20L8'

		&	EN ≥ 1
		40 X 64	7
			7
		20 x	7
	14	20
	I
			7

O

O

I/O

I/O

6	20	7	I/O
		7	I/O
		7	I/O
		7	I/O
		6

	TIBPAL20R4'
OE				EN 2
CLK				C1
	&	8	≥ 1	I = 0 2	Q
	40 X 64			1D
		8			Q
	20 x	8			Q
12
	20
I		8			Q
4
		7	EN ≥ 1		I/O
4	20
		7			I/O
		7			I/O
		7			I/O
		4
		4

denotes fused inputs

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

3

TIBPAL20R6-5C, TIBPAL20R8-5C

TIBPAL20R6-7M, TIBPAL20R8-7M HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS

SRPS010F ± D3353, OCTOBER 1989 ± REVISED SEPTEMBER 1992

functional block diagrams (positive logic)

TIBPAL20R6'

OE				EN 2
CLK				C1
	&	8	≥ 1	I = 0 2
	40 X 64			1D
		8
	20 x	8
12
	20
I		8
6
		8
2	20
		8
		7	EN ≥ 1
		7
		2
			6

		TIBPAL20R8'
OE				EN 2
CLK				C1
	&	8	≥ 1	I = 0 2
	40 X 64			1D
		8
	20 x	8
12
	20
I		8
		8
8	20
		8

8

8

8

denotes fused inputs

Q

Q

Q

Q

Q

Q

I/O

I/O

Q

Q

Q

Q

Q

Q

Q

Q

4	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TIBPAL20L8-5C

TIBPAL20L8-7M

HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS

SRPS010F ± D3353, OCTOBER 1989 ± REVISED SEPTEMBER 1992

logic diagram (positive logic)

1
I						Increment
	0	4	8	12	16	20	24	28	32	36	39
2											23
I											I
First Fuse
Numbers
	0
	40
	80										22
	120
	160										O
	200
	240
3	280
I

	320
	360
	400	21
	440
	480	I/O
	520
	560
4	600
I
	640
	680
	720	20
	760
	800	I/O
	840
	880
5	920
I
	960
	1000
	1040	19
	1080
	1120	I/O
	1160
	1200
6	1240
I
	1280
	1320
	1360	18
	1400
	1440	I/O
	1480
	1520
7	1560
I
	1600
	1640
	1680	17
	1720
	1760	I/O
	1800
	1840
8	1880
I
	1920
	1960
	2000	16
	2040
	2080	I/O
	2120
	2160
9	2200
I
	2240
	2280
	2320	15
	2360
	2400	O
	2440
	2480
10 2520		14
I		I
11		13
I		I

Fuse number = First fuse number + Increment

Pin numbers shown are for JT and NT packages.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

5

TIBPAL20R4-5C

TIBPAL20R4-7M

HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS

SRPS010F ± D3353, OCTOBER 1989 ± REVISED SEPTEMBER 1992

logic diagram (positive logic)

1

CLK

Increment

0

4

8

12

16

20

24

28

32

36

39

2

I

First Fuse

Numbers

0

40

80

120

160

200

240

3 280

I

320

360

400

440

480

520

560

4 600

I

640

680

720

760

800

840

880

5 920

I

960

1000

1040

1080

1120

1160

1200

6 1240

I

1280

1320

1360

1400

1440

1480

1520

7 1560

I

1600

1640

1680

1720

1760

1800

1840

8 1880

I

1920

1960

2000

2040

2080

2120

2160

9 2200

I

2240

2280

2320

2360

2400

2440

2480

10 2520

I

11

I

Fuse number = First fuse number + Increment

Pin numbers shown are for JT and NT packages.

23

I

22

I/O

21

I/O

	I = 0	20
	1D	Q
	C1
	I = 0	19
	1D
		Q
	C1
	I = 0	18
	1D
		Q
	C1
	I = 0	17
	1D
		Q
	C1

16

I/O

15

I/O

14

I

13

OE

6	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TIBPAL20R6-5C

TIBPAL20R6-7M

HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS

SRPS010F ± D3353, OCTOBER 1989 ± REVISED SEPTEMBER 1992

logic diagram (positive logic)

1

CLK

Increment

0

4

8

12

16

20

24

28

32

36

39

2

I

First Fuse

Numbers

0

40

80

120

160

200

240

3 280

I

320

360

400

440

480

520

560

4 600

I

640

680

720

760

800

840

880

5 920

I

960

1000

1040

1080

1120

1160

1200

6 1240

I

1280

1320

1360

1400

1440

1480

1520

7 1560

I

1600

1640

1680

1720

1760

1800

1840

8 1880

I

1920

1960

2000

2040

2080

2120

2160

9 2200

I

2240

2280

2320

2360

2400

2440

2480

10 2520

I

11

I

Fuse number = First fuse number + Increment

Pin numbers shown are for JT and NT packages.

23

I

22

I/O

	I = 0	21
	1D
		Q
	C1
	I = 0	20
	1D
		Q
	C1
	I = 0	19
	1D
		Q
	C1
	I = 0	18
	1D
		Q
	C1
	I = 0	17
	1D
		Q
	C1
	I = 0	16
	1D
		Q
	C1

15

I/O

14

I

13

OE

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

7

TIBPAL20R8-5C

TIBPAL20R8-7M

HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS

SRPS010F ± D3353, OCTOBER 1989 ± REVISED SEPTEMBER 1992

logic diagram (positive logic)

1

CLK

Increment

0

4

8

12

16

20

24

28

32

36

39

2

I

First Fuse

Numbers

0

40

80

120

160

200

240

3 280

I

320

360

400

440

480

520

560

4 600

I

640

680

720

760

800

840

880

5 920

I

960

1000

1040

1080

1120

1160

1200

6 1240

I

1280

1320

1360

1400

1440

1480

1520

7 1560

I

1600

1640

1680

1720

1760

1800

1840

8 1880

I

1920

1960

2000

2040

2080

2120

2160

9 2200

I

2240

2280

2320

2360

2400

2440

2480

10 2520

I

11

I

Fuse number = First fuse number + Increment

Pin numbers shown are for JT and NT packages.

		23
		I
	I = 0	22
	1D
		Q
	C1
	I = 0	21
	1D
		Q
	C1
	I = 0	20
	1D
		Q
	C1
	I = 0	19
	1D
		Q
	C1
	I = 0	18
	1D
		Q
	C1
	I = 0	17
	1D
		Q
	C1
	I = 0	16
	1D
		Q
	C1
	I = 0	15
	1D
		Q
	C1

14

I

13

OE

8	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TIBPAL20L8-5C

HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS

SRPS010F ± D3353, OCTOBER 1989 ± REVISED SEPTEMBER 1992

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V

Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±65°C to 150°C

NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle.

recommended operating conditions

		MIN	NOM	MAX	UNIT
VCC	Supply voltage	4.75	5	5.25	V
VIH	High-level input voltage (see Note 2)	2		5.5	V
VIL	Low-level input voltage (see Note 2)			0.8	V
IOH	High-level output current			± 3.2	mA
IOL	Low-level output current			24	mA
TA	Operating free-air temperature	0	25	75	°C

NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester noise. Testing these parameters should not be attempted without suitable equipment.

electrical characteristics over recommended operating free-air temperature range

PARAMETER

TEST CONDITIONS

MIN

TYP²

MAX

UNIT

VIK

VCC = 4.75 V,

II = ± 18 mA

± 0.8

± 1.5

V

VOH

VCC = 4.75 V,

IOH = ± 3.2 mA

2.4

2.7

V

VOL

VCC = 4.75 V,

IOL = 24 mA

0.3

0.5

V

IOZH³

VCC = 5.25 V,

VO = 2.7 V

100

µA

IOZL³

VCC = 5.25 V,

VO = 0.4 V

±100

µA

II

VCC = 5.25 V,

VI = 5.5 V

100

µA

IIH³

VCC = 5.25 V,

VI = 2.7 V

25

µA

I

³

V

CC

= 5.25 V,

V = 0.4 V

±250

µA

IL

I

IOS§

VCC = 5.25 V,

VO = 0.5 V

± 30

±70

±130

mA

ICC

VCC = 5.25 V,

VI = 0,

Outputs open

210

mA

Ci

f = 1 MHz,

VI = 2 V

8.5

pF

Co

f = 1 MHz,

VO = 2 V

10

pF

²

All typical values are at V

CC

= 5 V, T = 25°C.

³

A

I/O leakage is the worst case of IOZL and IIL or IOZH and IIH, respectively.

§Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to avoid test problems caused by test equipment ground degradation.

switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

	FROM		TO	TEST	TIBPAL20L8-5CFN		TIBPAL20L8-5CJT
PARAMETER							TIBPAL20L8-5CNT		UNIT
	(INPUT)		(OUTPUT)	CONDITIONS
					MIN	MAX	MIN	MAX
	I, I/O	O, I/O	with up to 4 outputs		1.5	5	1.5	5
			switching
tpd									ns
				R1 = 200 Ω,
	I, I/O	O, I/O	with more than 4		1.5	5	1.5	5.5
				R2 = 200 Ω,
			outputs switching
				See Figure 8
ten	I, I/O		O, I/O		2	7	2	7	ns
tdis	I, I/O		O, I/O		2	7	2	7	ns
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
			POST OFFICE BOX 655303 •DALLAS, TEXAS 75265						9