Texas Instruments TIBPAL20R8-25CNT, TIBPAL20R8-25CFN, TIBPAL20L8-25CFN, TIBPAL20R4-25CFN, TIBPAL20R4-25CNT Datasheet

TIBPAL20L8-25C, TIBPAL20R4-25C, TIBPAL20R6-25C, TIBPAL20R8-25C LOW-POWER HIGH-PERFORMANCE IMPACT PAL CIRCUITS

SRPS022 ± D2920, MAY 1987 ± REVISED MARCH 1992

	• Low-Power, High-Performance		TIBPAL20L8'
		JT OR NT PACKAGE
	Reduced ICC of 105 mA Max
				(TOP VIEW)
	fmax:
	Without Feedback . . . 33 MHz Min	I		1	24			VCC
	With Feedback . . . 25 MHz Min
		I		2	23			I
	tpd . . . 25 ns Max
		I		3	22			O
	• Direct Replacement for PAL20L8A,	I		4	21			I/O
	PAL20R4A, PAL20R6A, PAL20L8A, with at	I		5	20			I/O
	Least 50% Reduction in Power	I		6	19			I/O
	• Preload Capability on Output Registers	I		7	18			I/O
		I		8	17			I/O
	Simplifies Testing
		I		9	16			I/O
	• Power-Up Clear on Registered Devices (All
		I		10	15			O
	Register Outputs are Set Low, but Voltage	I		11	14			I
	Levels at the Output Pins Go High)	GND		12	13			I
	• Package Options Include Plastic Chip
				TIBPAL20L8'
	Carriers in Addition to Plastic and Ceramic
	DIPs		FN PACKAGE

•Dependable Texas Instruments Quality and Reliability

(TOP VIEW)
I I I NC	CC	O
	V I

			I		3-STATE	REGISTERED		I/O
	DEVICE							PORT			4			3 2				1		28 27 26
			INPUTS		O OUTPUTS	Q OUTPUTS
								S	I		5									25							I/O
									I		6																I/O
	PAL20L8		14		2		0	6												24
											7
	PAL20R4		12		0	4 (3-state buffers)		4	I											23							I/O
	PAL20R6		12		0	6 (3-state buffers)		2	NC		8									22							NC
	PAL20R8		12		0	8 (3-state buffers)		0	I		9									21							I/O
description									I		10									20							I/O
									I		11									19							I/O
	These programmable array logic devices feature										12 13 14							15 16 17 18
												I		I GND				NC		I I O
	high speed and functional equivalency when
	compared with currently available devices. These
	IMPACT			circuits combine			the	latest	NC ± No internal connection
	AdvancedLow-Power Schottky technology with
	proven titanium-tungsten fuses to provide reliable,								Pin assignments in operating mode
	high-performance substitutes for						conventional

TTL logic. Their easy programmability allows forquick design of custom functions and typically results in a more compact circuit board. In addition, chip carriers are available for futher reduction in board space.

All of the register outputs are set to a low level during power-up. Extra circuitry has been provided to allow loading of each register asynchronously to either a high or low state. This feature simplifies testing because the registers can be set to an initial state prior to executing the test sequence.

The TIBPAL20' C series is characterized from 0°C to 75°C.

These devices are covered by U.S. Patent 4,410,987

IMPACT is a trademark of Texas Instruments Incorporated.

PAL is a registered trademark of Advanced Micro Devices Inc.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

Copyright 1992, Texas Instruments Incorporated

1

TIBPAL20R4-25C, TIBPAL20R6-25C, TIBPAL20R8-25C

LOW-POWER HIGH-PERFORMANCE IMPACT PAL CIRCUITS

SRPS022 ± D2920, MAY 1987 ± REVISED MARCH 1992
TIBPAL20R4'						TIBPAL20R4'
JT OR NT PACKAGE						FN PACKAGE
	(TOP VIEW)					(TOP VIEW)
CLK	1	24	VCC				CLK	NC	CC	I/O
					I	I			V I
I	2	23	I
I	3	22	I/O		4	3	2	1	28 27 26
I	4	21	I/O	I	5					25	I/O
I	5	20	Q	I	6					24	Q
I	6	19	Q	I	7					23	Q
I	7	18	Q	NC	8					22	NC
I	8	17	Q
				I	9					21	Q
I	9	16	I/O
				I	10					20	Q
I	10	15	I/O
				I	11					19	I/O
I	11	14	I
					12 13 14 15 16 17 18
GND	12	13	OE
					I	I	GND	NC	OE I	I/O
TIBPAL20R6'						TIBPAL20R6'
JT OR NT PACKAGE						FN PACKAGE
	(TOP VIEW)					(TOP VIEW)
CLK	1	24	VCC		I		CLK	NC	CC	I/O
						I			V I
I	2	23	I
I	3	22	I/O		4	3	2	1	28 27 26
I	4	21	Q	I	5					25	Q
I	5	20	Q	I	6					24	Q
I	6	19	Q	I	7					23	Q
I	7	18	Q	NC	8					22	NC
I	8	17	Q	I	9					21	Q
I	9	16	Q
				I	10					20	Q
I	10	15	I/O
				I	11					19	Q
I	11	14	I
					12 13 14 15 16 17 18
GND	12	13	OE
					I	I	GND	NC	OE I	I/O
TIBPAL20R8'						TIBPAL20R8'
JT OR NT PACKAGE						FN PACKAGE
	(TOP VIEW)					(TOP VIEW)
CLK	1	24	VCC				CLK	NC	CC	Q
					I	I			V I
I	2	23	I
I	3	22	Q		4	3	2	1	28 27 26
I	4	21	Q	I	5					25	Q
I	5	20	Q	I	6					24	Q
I	6	19	Q	I	7					23	Q
I	7	18	Q	NC	8					22	NC
I	8	17	Q	I	9					21	Q
I	9	16	Q
				I	10					20	Q
I	10	15	Q
				I	11					19	Q
I	11	14	I
					12 13 14 15 16 17 18
GND	12	13	OE
					I	I	GND	NC	OE I	Q

Pin assignments in operating mode	NC ± No internal connection

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TIBPAL20L8-25C, TIBPAL20R4-25C

LOW-POWER HIGH-PERFORMANCE IMPACT PAL CIRCUITS

SRPS022 ± D2920, MAY 1987 ± REVISED MARCH 1992

functional block diagrams (positive logic)

TIBPAL20L8'

14	20 x
	20

I

6

20

OE

CLK

12	20 x
	20
I
4
4	20

&	EN ≥ 1
40 X 64 7	O
7	O
7	I/O
7	I/O
7	I/O
7	I/O
7	I/O
7	I/O
6

TIBPAL20R4'
			EN 2
			C1
&	8	≥ 1	I = 0 2
40 X 64			1D
	8

8

8

EN ≥ 1

7

7

7

7

4

4

Q

Q

Q

Q

I/O

I/O

I/O

I/O

denotes fused inputs

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

3

TIBPAL20R6-25C, TIBPAL20R8-25C

LOW-POWER HIGH-PERFORMANCE IMPACT PAL CIRCUITS

SRPS022 ± D2920, MAY 1987 ± REVISED MARCH 1992

functional block diagrams (positive logic)

TIBPAL20R6'

OE				EN 2
CLK				C1
	&	8	≥ 1	I = 0 2
	40 X 64			1D
		8
	20 x	8
12
	20
I		8
6
		8
2	20
		8
		7	EN ≥ 1
		7
		2
			6

		TIBPAL20R8'
OE				EN 2
CLK				C1
	&	8	≥ 1	I = 0 2
	40 X 64			1D
		8
	20 x	8
12
	20
I		8
		8
8	20
		8

8

8

8

denotes fused inputs

Q

Q

Q

Q

Q

Q

I/O

I/O

Q

Q

Q

Q

Q

Q

Q

Q

4	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TIBPAL20L8-25C

LOW-POWER HIGH-PERFORMANCE IMPACT PAL CIRCUITS

SRPS022 ± D2920, MAY 1987 ± REVISED MARCH 1992

logic diagram (positive logic)

1
I						Increment
	0	4	8	12	16	20	24	28	32	36	39
2											23
I											I
First Fuse
Numbers
	0
	40
	80										22
	120
	160										O
	200
	240
3	280
I

	320
	360
	400	21
	440
	480	I/O
	520
	560
4	600
I
	640
	680
	720	20
	760
	800	I/O
	840
	880
5	920
I
	960
	1000
	1040	19
	1080
	1120	I/O
	1160
	1200
6	1240
I
	1280
	1320
	1360	18
	1400
	1440	I/O
	1480
	1520
7	1560
I
	1600
	1640
	1680	17
	1720
	1760	I/O
	1800
	1840
8	1880
I
	1920
	1960
	2000	16
	2040
	2080	I/O
	2120
	2160
9	2200
I
	2240
	2280
	2320	15
	2360
	2400	O
	2440
	2480
10 2520		14
I		I
11		13
I		I

Fuse number = First fuse number + Increment

Pin numbers shown are for JT and NT packages.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

5

TIBPAL20R4-25C

LOW-POWER HIGH-PERFORMANCE IMPACT PAL CIRCUITS

SRPS022 ± D2920, MAY 1987 ± REVISED MARCH 1992

logic diagram (positive logic)

1

CLK

Increment

0

4

8

12

16

20

24

28

32

36

39

2

I

First Fuse

Numbers

0

40

80

120

160

200

240

3 280

I

320

360

400

440

480

520

560

4 600

I

640

680

720

760

800

840

880

5 920

I

960

1000

1040

1080

1120

1160

1200

6 1240

I

1280

1320

1360

1400

1440

1480

1520

7 1560

I

1600

1640

1680

1720

1760

1800

1840

8 1880

I

1920

1960

2000

2040

2080

2120

2160

9 2200

I

2240

2280

2320

2360

2400

2440

2480

10 2520

I

11

I

Fuse number = First fuse number + Increment

Pin numbers shown are for JT and NT packages.

23

I

22

I/O

21

I/O

	I = 0	20
	1D	Q
	C1
	I = 0	19
	1D
		Q
	C1
	I = 0	18
	1D
		Q
	C1
	I = 0	17
	1D
		Q
	C1

16

I/O

15

I/O

14

I

13

OE

6	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265