Texas Instruments CD4051BPWR, CD4051BPW, CD4051BNSR, CD4051BM96, CD4051BM Datasheet
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CD4051B, CD4052B, CD4053B
Data sheet acquired from Harris Semiconductor SCHS047D
August 1998 - Revised March 2000
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CMOS Analog Multiplexers/Demultiplexers |
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with Logic Level Conversion |
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The CD4051B, CD4052B, and CD4053B analog multiplexers |
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are digitally-controlled analog switches having low ON |
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[ /Title |
impedance and very low OFF leakage current. Control of |
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analog signals up to 20VP-P can be achieved by digital |
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(CD405 |
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signal amplitudes of 4.5V to 20V (if VDD -VSS = 3V, a |
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1B, |
VDD -VEE of up to 13V can be controlled; for VDD -VEE level |
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CD4052 |
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differences above 13V, a VDD -VSS of at least 4.5V is |
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B, |
required). For example, if VDD = +4.5V, VSS = 0V, and |
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CD4053 |
VEE = -13.5V, analog signals from -13.5V to +4.5V can be |
B)controlled by digital inputs of 0V to 5V. These multiplexer
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circuits dissipate extremely low quiescent power over the |
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full VDD -VSS and VDD -VEE supply-voltage ranges, |
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ject |
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independent of the logic state of the control signals. When |
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(CMOS |
a logic “1” is present at the inhibit input terminal, all |
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Analog |
channels are off. |
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Multi- |
The CD4051B is a single 8-Channel multiplexer having three |
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plex- |
binary control inputs, A, B, and C, and an inhibit input. The |
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ers/Dem |
three binary signals select 1 of 8 channels to be turned on, |
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ultiplex- |
and connect one of the 8 inputs to the output. |
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ers with |
The CD4052B is a differential 4-Channel multiplexer having |
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Logic |
two binary control inputs, A and B, and an inhibit input. The |
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Level |
two binary input signals select 1 of 4 pairs of channels to be |
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Conver- |
turned on and connect the analog inputs to the outputs. |
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sion) |
The CD4053B is a triple 2-Channel multiplexer having three |
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/Author |
separate digital control inputs, A, B, and C, and an inhibit |
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() |
input. Each control input selects one of a pair of channels |
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which are connected in a single-pole, double-throw |
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configuration. |
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words |
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When these devices are used as demultiplexers, the |
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(Harris |
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“CHANNEL IN/OUT” terminals are the outputs and the |
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Semi- |
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“COMMON OUT/IN” terminals are the inputs. |
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conduc- |
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tor, |
Ordering Information |
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CD4000 |
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TEMP. RANGE |
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PART NUMBER |
(oC) |
PACKAGE |
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CD4051BF, CD4052BF, |
-55 to 125 |
16 Ld CERAMIC |
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CD4053BF |
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DIP |
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CD4051BE, CD4052BE, |
-55 to 125 |
16 Ld PDIP |
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CD4053BE |
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CD4051BM, CD4051BNS |
-55 to 125 |
16 Ld SOIC |
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CD4051BPW, CD4052BPW, |
-55 to 125 |
16 Ld TSSOP |
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CD4053BPW |
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Features
•Wide Range of Digital and Analog Signal Levels
-Digital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 20V
-Analog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤20VP-P
•Low ON Resistance, 125Ω (Typ) Over 15VP-P Signal Input Range for VDD-VEE = 18V
•High OFF Resistance, Channel Leakage of ±100pA (Typ) at VDD-VEE = 18V
•Logic-Level Conversion for Digital Addressing Signals of
3V to 20V (VDD-VSS = 3V to 20V) to Switch Analog Signals to 20VP-P (VDD-VEE = 20V)
•Matched Switch Characteristics, rON = 5Ω (Typ) for VDD-VEE = 15V
•Very Low Quiescent Power Dissipation Under All DigitalControl Input and Supply Conditions, 0.2µW (Typ) at VDD-VSS = VDD-VEE = 10V
•Binary Address Decoding on Chip
•5V, 10V and 15V Parametric Ratings
•10% Tested for Quiescent Current at 20V
•Maximum Input Current of 1µA at 18V Over Full Package Temperature Range, 100nA at 18V and 25oC
•Break-Before-Make Switching Eliminates Channel Overlap
Applications
•Analog and Digital Multiplexing and Demultiplexing
•A/D and D/A Conversion
•Signal Gating
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. |
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Copyright © 2000, Texas Instruments Incorporated |
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CD4051B, CD4052B, CD4053B
Pinouts
CD4051B (PDIP, CDIP, SOIC, TSSOP) |
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CD4052B (PDIP, CDIP, TSSOP) |
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TOP VIEW |
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TOP VIEW |
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CHANNELS |
4 |
1 |
16 |
VDD |
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Y CHANNELS |
0 |
1 |
16 |
VDD |
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IN/OUT |
6 |
2 |
15 |
2 |
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IN/OUT |
2 |
2 |
15 |
2 |
X CHANNELS |
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COM OUT/IN |
3 |
14 |
1 |
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COMMON “Y” OUT/IN |
3 |
14 |
1 |
IN/OUT |
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CHANNELS IN/OUT |
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CHANNELS |
7 |
4 |
13 |
0 |
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Y CHANNELS |
3 |
4 |
13 |
COMMON “X” OUT/IN |
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IN/OUT |
5 |
5 |
12 |
3 |
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IN/OUT |
1 |
5 |
12 |
0 |
X CHANNELS |
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INH |
6 |
11 |
A |
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INH |
6 |
11 |
3 |
IN/OUT |
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VEE |
7 |
10 |
B |
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VEE |
7 |
10 |
A |
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VSS |
8 |
9 |
C |
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VSS |
8 |
9 |
B |
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CD4053B (PDIP, CDIP, TSSOP) |
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TOP VIEW |
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by |
1 |
16 |
VDD |
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IN/OUT bx |
2 |
15 |
OUT/IN bx OR by |
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cy |
3 |
14 |
OUT/IN ax OR ay |
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OUT/IN CX OR CY |
4 |
13 |
ay |
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IN/OUT CX |
5 |
12 |
IN/OUT |
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ax |
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INH |
6 |
11 |
A |
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VEE |
7 |
10 |
B |
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VSS |
8 |
9 |
C |
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Functional Block Diagrams
CD4051B
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CHANNEL IN/OUT |
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7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
16 VDD |
4 |
2 |
5 |
1 |
12 |
15 |
14 |
13 |
A † |
11 |
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B † |
10 |
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BINARY |
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LOGIC |
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TO |
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1 OF 8 |
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LEVEL |
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DECODER |
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CONVERSION |
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C † |
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WITH |
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INHIBIT |
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INH † |
6 |
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TG |
TG |
TG |
TG |
COMMON |
OUT/IN |
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3 |
TG |
TG |
TG |
TG |
8 VSS |
7 VEE |
† All inputs are protected by standard CMOS protection network.
2
CD4051B, CD4052B, CD4053B
Functional Block Diagrams (Continued)
CD4052B
X CHANNELS IN/OUT 3 2 1 0 11 15 14 12
16 VDD
A † |
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BINARY |
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LOGIC |
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B † |
9 |
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1 OF 4 |
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LEVEL |
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CONVERSION |
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DECODER |
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WITH |
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INH † |
6 |
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INHIBIT |
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8 VSS |
7 VEE |
TG |
TG |
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TG |
COMMON X |
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OUT/IN |
TG |
13 |
TG |
3 |
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COMMON Y |
TG |
OUT/IN |
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TG |
TG |
1 |
5 |
2 |
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0 |
1 |
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3 |
Y CHANNELS IN/OUT
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CD4053B |
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BINARY TO |
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LOGIC |
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1 OF 2 |
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IN/OUT |
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16 VDD |
DECODERS |
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LEVEL |
WITH |
cy |
cx |
by |
bx |
ay |
ax |
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CONVERSION |
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INHIBIT |
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3 |
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1 |
2 |
13 |
12 |
COMMON |
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OUT/IN |
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TG |
ax OR ay |
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14 |
A † |
11 |
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TG |
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COMMON |
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TG |
OUT/IN |
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bx OR by |
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B † |
10 |
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15 |
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TG |
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COMMON |
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TG |
OUT/IN |
C † |
9 |
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cx OR cy |
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4 |
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TG |
INH † 6
VDD
8 VSS |
7 VEE |
† All inputs are protected by standard CMOS protection network.
3
CD4051B, CD4052B, CD4053B
TRUTH TABLES
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INPUT STATES |
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INHIBIT |
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C |
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B |
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A |
“ON” CHANNEL(S) |
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CD4051B |
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0 |
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0 |
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0 |
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0 |
0 |
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0 |
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0 |
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0 |
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1 |
1 |
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0 |
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0 |
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1 |
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0 |
2 |
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0 |
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0 |
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1 |
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1 |
3 |
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0 |
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1 |
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0 |
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0 |
4 |
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0 |
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1 |
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0 |
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1 |
5 |
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0 |
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1 |
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1 |
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0 |
6 |
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0 |
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1 |
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1 |
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1 |
7 |
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1 |
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X |
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X |
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None |
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CD4052B |
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INHIBIT |
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B |
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A |
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0 |
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0 |
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0 |
0x, 0y |
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0 |
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0 |
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1 |
1x, 1y |
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0 |
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1 |
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2x, 2y |
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0 |
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1 |
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3x, 3y |
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1 |
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X |
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None |
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CD4053B |
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INHIBIT |
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A OR B OR C |
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0 |
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0 |
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ax or bx or cx |
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0 |
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1 |
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ay or by or cy |
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1 |
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X |
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None |
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X = Don’t Care
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