November 1994
54F/74F194
4-Bit Bidirectional Universal Shift Register
General Description
The 'F194 is a high-speed 4-bit bidirectional universal shift register. As a high-speed, multifunctional, sequential building block, it is useful in a wide variety of applications. It may be used in serial-serial, shift left, shift right, serial-parallel, parallel-serial, and parallel-parallel data register transfers. The 'F194 is similar in operation to the 'F195 universal shift register, with added features of shift left without external connections and hold (do nothing) modes of operation.
Features
YTypical shift frequency of 150 MHz
YAsynchronous master reset
YHold (do nothing) mode
YFully synchronous serial or parallel data transfers
Commercial |
Military |
Package |
Package Description |
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Number |
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74F194PC |
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N16E |
16-Lead (0.300× Wide) Molded Dual-In-Line |
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54F194DM (Note 2) |
J16A |
16-Lead Ceramic Dual-In-Line |
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74F194SC (Note 1) |
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M16A |
16-Lead (0.150× Wide) Molded Small Outline, JEDEC |
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74F194SJ (Note 1) |
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M16D |
16-Lead (0.300× Wide) Molded Small Outline, EIAJ |
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54F194FM (Note 2) |
W16A |
16-Lead Cerpack |
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54F194LM (Note 2) |
E20A |
20-Lead Ceramic Leadless Chip Carrier, Type C |
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Note 1: Devices also available in 13× reel. Use suffix e SCX and SJX.
Note 2: Military grade device with environmental and burn-in processing. Use suffix e DMQB, FMQB and LMQB.
Logic Symbols |
Connection Diagrams |
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IEEE/IEC |
Pin Assignment for |
Pin Assignment |
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DIP, SOIC and Flatpak |
for LCC |
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TL/F/9498 ± 1
TL/F/9498 ± 2
TL/F/9498 ± 5
TL/F/9498 ± 3
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C1995 National Semiconductor Corporation |
TL/F/9498 |
RRD-B30M105/Printed in U. S. A. |
Register Shift Universal Bidirectional Bit-4 54F/74F194
Unit Loading/Fan Out
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Pin |
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54F/74F |
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Description |
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U.L. |
Input IIH/IIL |
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Names |
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HIGH/LOW |
Output IOH/IOL |
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S0, S1 |
Mode Control Inputs |
1.0/1.0 |
20 mA/b0.6 mA |
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P0 ± P3 |
Parallel Data Inputs |
1.0/1.0 |
20 mA/b0.6 mA |
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DSR |
Serial Data Input (Shift Right) |
1.0/1.0 |
20 mA/b0.6 mA |
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DSL |
Serial Data Input (Shift Left) |
1.0/1.0 |
20 mA/b0.6 mA |
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CP |
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Clock Pulse Input (Active Rising Edge) |
1.0/1.0 |
20 mA/b0.6 mA |
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MR |
Asynchronous Master Reset Input (Active LOW) |
1.0/1.0 |
20 mA/b0.6 mA |
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Q0 ± Q3 |
Parallel Outputs |
50/33.3 |
b1 mA/20 mA |
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Functional Description
The 'F194 contains four edge-triggered D flip-flops and the necessary interstage logic to synchronously perform shift right, shift left, parallel load and hold operations. Signals applied to the Select (S0, S1) inputs determine the type of operation, as shown in the Mode Select Table. Signals on the Select, Parallel data (P0 ± P3) and Serial data (DSR, DSL)
inputs can change when the clock is in either state, provided only that the recommended setup and hold times, with respect to the clock rising edge, are observed. A LOW signal on Master Reset (MR) overrides all other inputs and forces the outputs LOW.
Mode Select Table
Operating |
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Inputs |
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Outputs |
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Mode |
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MR |
S1 |
S0 |
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DSR |
DSL |
Pn |
Q0 |
Q1 |
Q2 |
Q3 |
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Reset |
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L |
X |
X |
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X |
X |
X |
L |
L |
L |
L |
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Hold |
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H |
l |
l |
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X |
X |
X |
q0 |
q1 |
q2 |
q3 |
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Shift Left |
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H |
h |
l |
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X |
l |
X |
q1 |
q2 |
q3 |
L |
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H |
h |
l |
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X |
h |
X |
q1 |
q2 |
q3 |
H |
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Shift Right |
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H |
l |
h |
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l |
X |
X |
L |
q0 |
q1 |
q2 |
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H |
l |
h |
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h |
X |
X |
H |
q0 |
q1 |
q2 |
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Parallel Load |
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H |
h |
h |
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X |
X |
pn |
p0 |
p1 |
p2 |
p3 |
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H (h) e High Voltage Level
L (l) e Low Voltage Level
pn (qn) e Lower case letters indicate the state of the referenced input (or output) one setup time prior to the LOW-to-HIGH clock transition. X e Immaterial
Logic Diagram
TL/F/9498 ± 4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature |
b65§C to a150§C |
Ambient Temperature under Bias |
b55§C to a125§C |
Junction Temperature under Bias |
b55§C to a175§C |
Plastic |
b55§C to a150§C |
VCC Pin Potential to |
b0.5V to a7.0V |
Ground Pin |
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Input Voltage (Note 2) |
b0.5V to a7.0V |
Input Current (Note 2) |
b30 mA to a5.0 mA |
Voltage Applied to Output |
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in HIGH State (with VCC e 0V) |
b0.5V to VCC |
Standard Output |
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TRI-STATEÉ Output |
b0.5V to a5.5V |
Current Applied to Output |
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in LOW State (Max) |
twice the rated IOL (mA) |
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature |
b55§C to a125§C |
Military |
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Commercial |
0§C to a70§C |
Supply Voltage |
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Military |
a4.5V to a5.5V |
Commercial |
a4.5V to a5.5V |
DC Electrical Characteristics
Symbol |
Parameter |
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54F/74F |
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Units |
VCC |
Conditions |
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Min |
Typ |
Max |
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VIH |
Input HIGH Voltage |
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2.0 |
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V |
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Recognized as a HIGH Signal |
VIL |
Input LOW Voltage |
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0.8 |
V |
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Recognized as a LOW Signal |
VCD |
Input Clamp Diode Voltage |
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b1.2 |
V |
Min |
IIN e b18 mA |
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VOH |
Output HIGH |
54F |
10% VCC |
2.5 |
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IOH e b1 mA |
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Voltage |
74F |
10% VCC |
2.5 |
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V |
Min |
IOH e b1 mA |
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74F |
5% VCC |
2.7 |
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IOH e b1 mA |
VOL |
Output LOW |
54F |
10% VCC |
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0.5 |
V |
Min |
IOL e 20 mA |
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Voltage |
74F |
10% VCC |
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0.5 |
IOL e 20 mA |
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IIH |
Input HIGH |
54F |
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20.0 |
mA |
Max |
VIN e 2.7V |
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Current |
74F |
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5.0 |
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IBVI |
Input HIGH Current |
54F |
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100 |
mA |
Max |
VIN e 7.0V |
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Breakdown Test |
74F |
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7.0 |
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ICEX |
Output HIGH |
54F |
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250 |
mA |
Max |
VOUT e VCC |
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Leakage Current |
74F |
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50 |
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VID |
Input Leakage |
74F |
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4.75 |
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V |
0.0 |
IID e 1.9 mA |
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Test |
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All Other Pins Grounded |
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IOD |
Output Leakage |
74F |
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3.75 |
mA |
0.0 |
VIOD e 150 mV |
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Circuit Current |
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All Other Pins Grounded |
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IIL |
Input LOW Current |
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b0.6 |
mA |
Max |
VIN e 0.5V |
IOS |
Output Short-Circuit Current |
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b60 |
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b150 |
mA |
Max |
VOUT e 0V |
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ICC |
Power Supply Current |
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33 |
46 |
mA |
Max |
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3
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