Motorola MCM6206BBEJ25, MCM6206BBEJ25R, MCM6206BBEJ12R, MCM6206BBEJ15R, MCM6206BBEJ20 Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document by MCM6206BB/D

Product Preview

32K x 8 Bit Fast Static RAM

The MCM6206BB is a 262,144 bit static random access memory organized as 32,768 words of 8 bits. Static design eliminates the need for external clocks or timing strobes, while CMOS circuitry reduces power consumption and provides for greater reliability.

This device meets JEDEC standards for functionality and pinout, and is available in plastic small±outline J±leaded packages.

•Single 5 V ± 10% Power Supply

•Fully Static Ð No Clock or Timing Strobes Necessary

•Fast Access Times: 12/15/20/25 ns

•Equal Address and Chip Enable Access Times

•Output Enable (G) Feature for Increased System Flexibility and to Eliminate Bus Contention Problems

•Low Power Operation: 125 ± 140 mA Maximum AC

•Fully TTL Compatible Ð Three State Output

		BLOCK DIAGRAM
A
A			VCC
A			VSS
A
A	ROW		MEMORY MATRIX
	DECODER
A
A
A
A
DQ		.
	INPUT	.	COLUMN I/O
		.
DQ	DATA
	CONTROL		COLUMN DECODER
E	CIRCUIT	A	A A A A A
W
	CONTROL
G

MCM6206BB

J PACKAGE 300 MIL SOJ CASE 810B±03

PIN ASSIGNMENT

A					VCC
		1	28
						W
A		2	27
A		3	26			A
A		4	25			A
A		5	24			A
A		6	23			A
						G
A		7	22
A		8	21			A
						E
A		9	20
A		10	19			DQ
DQ		11	18			DQ
DQ		12	17			DQ
DQ		13	16			DQ
VSS		14	15			DQ

PIN NAMES

A . . . . . . . . . . . . . . . . . . . . Address Input

DQ . . . . . . . . . . Data Input/Data Output

W . . . . . . . . . . . . . . . . . . . . Write Enable

G . . . . . . . . . . . . . . . . . . . Output Enable

E . . . . . . . . . . . . . . . . . . . . . . Chip Enable

VCC . . . . . . . . . . . Power Supply (+ 5 V)

VSS . . . . . . . . . . . . . . . . . . . . . . . Ground

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

6/4/97

MOTOROLA FAST SRAM	MCM6206BB
Motorola, Inc. 1997
	1

TRUTH TABLE (X = Don't Care)

E	G	W	Mode	VCC Current	Output	Cycle
H	X	X	Not Selected	ISB1, ISB2	High±Z	±
L	H	H	Output Disabled	ICCA	High±Z	±
L	L	H	Read	ICCA	Dout	Read Cycle
L	X	L	Write	ICCA	High±Z	Write Cycle

ABSOLUTE MAXIMUM RATINGS

Rating	Symbol	Value		Unit
Power Supply Voltage	VCC	± 0.5 to +	7.0	V
Voltage Relative to VSS For Any Pin	Vin, Vout	± 0.5 to VCC + 0.5		V
Except VCC
Output Current	Iout	± 20		mA
Power Dissipation	PD	1.0		W
Temperature Under Bias	Tbias	± 10 to +	85	°C
Ambient Temperature	TA	0 to + 70		°C
Storage TemperatureÐPlastic	Tstg	± 55 to + 125		°C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPER-

ATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high±impedance circuit.

This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.

DC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ±10%, TA = 0 to 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS

Parameter	Symbol	Min	Typ	Max	Unit
Supply Voltage (Operating Voltage Range)	VCC	4.5	5.0	5.5	V
Input High Voltage	VIH	2.2	Ð	VCC + 0.3**	V
Input Low Voltage	VIL	± 0.5*	Ð	0.8	V

*VIL (min) = ± 0.5 V dc; VIL (min) = ± 2.0 V ac (pulse width ≤ 20 ns)

**VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 20 ns)

DC CHARACTERISTICS

			Parameter		Symbol	Min	Max	Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC)					Ilkg(I)	Ð	± 1	μA
Output Leakage Current (E = VIH or G = VIH, Vout = 0 to VCC)					Ilkg(O)	Ð	± 1	μA
Output High Voltage (IOH = ± 4.0 mA)					VOH	2.4	Ð	V
Output Low Voltage (IOL = 8.0 mA)					VOL	Ð	0.4	V

POWER SUPPLY CURRENTS

Parameter

Symbol

± 12

± 15

± 20

± 25

Unit

AC Active Supply Current (Iout = 0 mA, VCC = Max, f = fmax)

ICCA

140

135

130

125

mA

AC Standby Current (E = VIH, VCC = Max, f = fmax)

ISB1

40

35

35

30

mA

CMOS Standby Current (VCC = Max, f = 0 MHz, E ≥ VCC ± 0.2 V

ISB2

10

10

10

10

mA

Vin ≤ VSS + 0.2 V, or ≥ VCC ± 0.2 V)

CAPACITANCE (f = 1 MHz, dV = 3 V, TA = 25°C, Periodically sampled rather than 100% tested)

Characteristic

Symbol

Max

Unit

Address Input Capacitance

Cin

6

pF

Control Pin Input Capacitance (E, G, W)

Cin

8

pF

I/O Capacitance

CI/O

8

pF

MCM6206BB	MOTOROLA FAST SRAM
2

AC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level . . . . . . . . .

. . . . .

. 1.5 V

Output Timing Measurement Reference Level . . .

. . . . . . . .

. . 1.5 V

Input Pulse Levels . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . .

. . 0 to 3.0 V

Output Load .

. . . . . .

. .

. . . . . . .

.

. Figure 1 Unless Otherwise Noted

Input Rise/Fall Time . . . . . . . . . . . . . . . . . .

. . . . . . . . . . .

. . . . .

. .

5 ns

READ CYCLE (See Note 1)

± 12

± 15

± 20

± 25

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Min

Max

Unit

Notes

Read Cycle Time

tAVAV

12

Ð

15

Ð

20

Ð

25

Ð

ns

2

Address Access Time

tAVQV

Ð

12

Ð

15

Ð

20

Ð

25

ns

Enable Access Time

tELQV

Ð

12

Ð

15

Ð

20

Ð

25

ns

3

Output Enable Access Time

tGLQV

Ð

6

Ð

8

Ð

10

Ð

12

ns

Output Hold from Address Change

tAXQX

3

Ð

3

Ð

3

Ð

3

Ð

ns

4,5,6

Enable Low to Output Active

tELQX

4

Ð

4

Ð

4

Ð

4

Ð

ns

4,5,6

Enable High to Output High±Z

tEHQZ

Ð

7

Ð

8

Ð

9

Ð

10

ns

4,5,6

Output Enable Low to Output Active

tGLQX

0

Ð

0

Ð

0

Ð

0

Ð

ns

4,5,6

Output Enable High to Output High±Z

tGHQZ

Ð

6

Ð

7

Ð

8

Ð

10

ns

4,5,6

Power Up Time

tELICCH

0

Ð

0

Ð

0

Ð

0

Ð

ns

Power Down Time

tEHICCL

Ð

12

Ð

15

Ð

20

Ð

25

ns

NOTES:

1.W is high for read cycle.

2.All timings are referenced from the last valid address to the first transitioning address.

3.Addresses valid prior to or coincident with E going low.

4.At any given voltage and temperature, tEHQZ (max) is less than tELQX (min), and tGHQZ (max) is less than tGLQX (min), both for a given device and from device to device.

5.Transition is measured ±500 mV from steady±state voltage.

6.This parameter is sampled and not 100% tested.

7.Device is continuously selected (E = VIL, G = VIL).

Z0 = 50 Ω

OUTPUT

50 Ω

VL = 1.5 V

TIMING LIMITS

The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time. On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.

Figure 1. AC Test Loads

MOTOROLA FAST SRAM	MCM6206BB
	3