Motorola MCM6205DJ15R2, MCM6205DJ15, MCM6205DJ25, MCM6205DJ20, MCM6205DJ20R2 Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document by MCM6205D/D

32K x 9 Bit Fast Static RAM

The MCM6205D is fabricated using Motorola's high±performance silicon±gate CMOS technology. Static design eliminates the need for external clocks or timing strobes, while CMOS circuitry reduces power consumption and provides for greater reliability.

This device meets JEDEC standards for functionality and pinout, and is available in a plastic small±outline J±leaded package.

•Single 5 V ± 10% Power Supply

•Fully Static Ð No Clock or Timing Strobes Necessary

•Fast Access Times: 15, 20, and 25 ns

•Equal Address and Chip Enable Access Times

•Output Enable (G) Feature for Increased System Flexibility and to Eliminate Bus Contention Problems

•Low Power Operation: 130 ± 140 mA Maximum AC

•Fully TTL Compatible Ð Three State Output

BLOCK DIAGRAM

A1								VCC
A3
								VSS
A4
A6	ROW			MEMORY MATRIX
				256 ROWS x
A7	DECODER
				128 x 9 COLUMNS
A9
A10
A11
DQ0	INPUT			COLUMN I/O
DQ8	DATA
	CONTROL			COLUMN DECODER
E1		A0	A2	A5	A8	A12	A13	A14
E2
W
G

MCM6205D

J PACKAGE 300 MIL SOJ CASE 857±02

PIN ASSIGNMENT

NC		1	32		VCC
NC		2	31			A14
A8		3	30		E2
A7		4	29			W
A6		5	28			A13
A5		6	27			A9
A4		7	26			A10
A3		8	25			A11
A2		9	24				G
A1		10	23			A12
A0		11	22			E1
DQ0		12	21			DQ8
DQ1		13	20			DQ7
DQ2		14	19			DQ6
DQ3		15	18			DQ5
VSS		16	17			DQ4

PIN NAMES

A0 ± A14 . . . . . . . . . . . . . Address Input

DQ0 ± DQ8 . . . Data Input/Data Output

W . . . . . . . . . . . . . . . . . . . . Write Enable

G . . . . . . . . . . . . . . . . . . . Output Enable

E1, E2 . . . . . . . . . . . . . . . . . Chip Enable

NC . . . . . . . . . . . . . . . . . No Connection

VCC . . . . . . . . . . . Power Supply (+ 5 V)

VSS . . . . . . . . . . . . . . . . . . . . . . . Ground

REV 1 5/95

Motorola, Inc. 1994

TRUTH TABLE (X = Don't Care)

E1

E2

G

W

Mode

VCC Current

Output

Cycle

H

X

X

X

Not Selected

ISB1, ISB2

High±Z

Ð

X

L

X

X

Not Selected

ISB1, ISB2

High±Z

Ð

L

H

H

H

Output Disabled

ICCA

High±Z

Ð

L

H

L

H

Read

ICCA

Dout

Read Cycle

L

H

X

L

Write

ICCA

High±Z

Write Cycle

ABSOLUTE MAXIMUM RATINGS

Rating	Symbol	Value		Unit
Power Supply Voltage	VCC	± 0.5 to +	7.0	V
Voltage Relative to VSS For Any Pin	Vin, Vout	± 0.5 to VCC + 0.5		V
Except VCC
Output Current	Iout	± 20		mA
Power Dissipation	PD	1.0		W
Temperature Under Bias	Tbias	± 10 to +	85	°C
Operating Temperature	TA	0 to + 70		°C
Storage Temperature Ð Plastic	Tstg	± 55 to + 125		°C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high±impedance circuit.

This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.

DC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS

Parameter	Symbol	Min	Typ	Max	Unit
Supply Voltage (Operating Voltage Range)	VCC	4.5	5.0	5.5	V
Input High Voltage	VIH	2.2	Ð	VCC + 0.3**	V
Input Low Voltage	VIL	± 0.5*	Ð	0.8	V

*VIL (min) = ± 0.5 V dc; VIL (min) = ± 2.0 V ac (pulse width ≤ 20 ns)

**VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 20 ns)

DC CHARACTERISTICS

		Parameter			Symbol	Min	Max	Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC)					Ilkg(I)	Ð	± 1	μA
Output Leakage Current		= VIH or		= VIH or E2 = VIL, Vout = 0 to VCC)	Ilkg(O)	Ð	± 1	μA
	(E1		G
Output High Voltage (IOH = ± 4.0 mA)					VOH	2.4	Ð	V
Output Low Voltage (IOL = 8.0 mA)					VOL	Ð	0.4	V

POWER SUPPLY CURRENTS

		Parameter			Symbol	± 15	± 20	± 25	Unit
AC Active Supply Current (Iout = 0 mA, VCC = Max, f = fmax)					ICCA	140	135	130	mA
AC Standby Current		= VIH, or E2 = VIL, VCC = Max, f = fmax)			ISB1	40	40	35	mA
	(E1
CMOS Standby Current (VCC = Max, f = 0 MHz,				≥ VCC ± 0.2 V or	ISB2	20	20	20	mA
			E1
E2 ≤ VSS + 0.2 V, Vin ≤ VSS + 0.2 V, or ≥ VCC ± 0.2 V)

MCM6205D	MOTOROLA FAST SRAM
2

CAPACITANCE (f = 1 MHz, dV = 3 V, TA = 25°C, Periodically sampled rather than 100% tested)

					Characteristic		Symbol	Max	Unit
Address Input Capacitance							Cin	6	pF
Control Pin Input Capacitance		E2,					Cin	8	pF
	(E1,		G, W)
I/O Capacitance							CI/O	8	pF

AC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level . . . . . . . . . . . .	. . . 1.5	V	Output Timing Measurement Reference Level . . . . . . . . . . . . .		1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	0 to 3.0	V	Output Load . . . . . . . . . . . . . . . .	Figure 1A Unless Otherwise Noted
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 5 ns

READ CYCLE (See Notes 1 and 2)

		MCM6205D±15		MCM6205D±20		MCM6205D±25
Parameter	Symbol	Min	Max	Min	Max	Min	Max	Unit	Notes
Read Cycle Time	tAVAV	15	Ð	20	Ð	25	Ð	ns	3
Address Access Time	tAVQV	Ð	15	Ð	20	Ð	25	ns
Enable Access Time	tELQV	Ð	15	Ð	20	Ð	25	ns	4
Output Enable Access Time	tGLQV	Ð	8	Ð	10	Ð	12	ns
Output Hold from Address Change	tAXQX	4	Ð	4	Ð	4	Ð	ns
Enable Low to Output Active	tELQX	4	Ð	4	Ð	4	Ð	ns	5, 6, 7
Enable High to Output High±Z	tEHQZ	0	8	0	9	0	10	ns	5, 6, 7
Output Enable Low to Output Active	tGLQX	0	Ð	0	Ð	0	Ð	ns	5, 6, 7
Output Enable High to Output High±Z	tGHQZ	0	7	0	8	0	10	ns	5, 6, 7
Power Up Time	tELICCH	0	Ð	0	Ð	0	Ð	ns
Power Down Time	tEHICCL	Ð	15	Ð	20	Ð	25	ns
NOTES:

1.W is high for read cycle.

2.E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E.

3.All timings are referenced from the last valid address to the first transitioning address.

4.Addresses valid prior to or coincident with E going low.

5.At any given voltage and temperature, tEHQZ (max) is less than tELQX (min), and tGHQZ (max) is less than tGLQX (min), both for a given device and from device to device.

6.Transition is measured ± 500 mV from steady±state voltage with load of Figure 1B.

7.This parameter is sampled and not 100% tested.

8.Device is continuously selected (E1 = VIL, E2 = VIH, G = VIL).

Z0 = 50 Ω

OUTPUT

AC TEST LOADS
			+ 5 V
			480 Ω
	OUTPUT
50 Ω	255	Ω	5 pF
VL = 1.5 V

Figure 1A

Figure 1B

TIMING LIMITS

The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.

MOTOROLA FAST SRAM	MCM6205D
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