MOTOROLA MC74VHC245ML2, MC74VHC245ML1, MC74VHC245DW, MC74VHC245DWR2, MC74VHC245M Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Octal Bus Transceiver

The MC74VHC245 is an advanced high speed CMOS octal bus transceiver fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.

It is intended for two±way asynchronous communication between data buses. The direction of data transmission is determined by the level of the DIR input. The output enable pin (OE) can be used to disable the device, so that the buses are effectively isolated.

All inputs are equipped with protection circuits against static discharge.

•High Speed: tPD = 4.0ns (Typ) at VCC = 5V

•Low Power Dissipation: ICC = 4μA (Max) at TA = 25°C

•High Noise Immunity: VNIH = VNIL = 28% VCC

•Power Down Protection Provided on Inputs

•Balanced Propagation Delays

•Designed for 2V to 5.5V Operating Range

•Low Noise: VOLP = 1.2V (Max)

•Pin and Function Compatible with Other Standard Logic Families

•Latchup Performance Exceeds 300mA

•ESD Performance: HBM > 2000V; Machine Model > 200V

•Chip Complexity: 308 FETs or 77 Equivalent Gates

APPLICATION NOTES

1.Do not force a signal on an I/O pin when it is an active output, damage may occur.

2.All floating (high impedence) input or I/O pins must be fixed by means of pull up or pull down resistors or bus terminator ICs.

3.A parasitic diode is formed between the bus and VCC terminals. Therefore, the VHC245 cannot be used to interface 5V to 3V systems directly.

LOGIC DIAGRAM

		A1	2	18	B1
		A2	3	17	B2
		A3	4	16	B3
	A A4		5	15	B4	B
	DATA	A5	6	14	B5	DATA
	PORT					PORT
			7	13
		A6			B6
		A7	8	12	B7
		A8	9	11	B8
		DIR	1
		OE	19

		FUNCTION TABLE
Control Inputs
			Operation
OE	DIR
L	L		Data Transmitted from Bus B to Bus A
L	H		Data Transmitted from Bus A to Bus B
H	X		Buses Isolated (High±Impedance State)

MC74VHC245

DW SUFFIX

20±LEAD SOIC PACKAGE

CASE 751D±04

DT SUFFIX

20±LEAD TSSOP PACKAGE

CASE 948E±02

M SUFFIX

20±LEAD SOIC EIAJ PACKAGE

CASE 967±01

ORDERING INFORMATION

MC74VHCXXXDW SOIC MC74VHCXXXDT TSSOP MC74VHCXXXM SOIC EIAJ

PIN ASSIGNMENT

DIR	1	20		VCC
A1	2	19	OE
A2	3	18	B1
A3	4	17	B2
A4	5	16	B3
A5	6	15		B4
A6	7	14		B5
A7	8	13		B6
A8	9	12		B7
GND	10	11		B8

6/97

Motorola, Inc. 1997

1

REV 1

MC74VHC245

MAXIMUM RATINGS*

Symbol	Parameter		Value	Unit
VCC	DC Supply Voltage		± 0.5 to + 7.0	V
Vin	DC Input Voltage		± 0.5 to + 7.0	V
Vout	DC Output Voltage		± 0.5 to VCC + 0.5	V
IIK	Input Diode Current		± 20	mA
IOK	Output Diode Current		± 20	mA
Iout	DC Output Current, per Pin		± 25	mA
ICC	DC Supply Current, VCC and GND Pins		± 75	mA
PD	Power Dissipation in Still Air	SOIC Packages²	500	mW
		TSSOP Package²	450
Tstg	Storage Temperature		± 65 to + 150	_C

*Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute±maximum±rated conditions is not implied.

²Derating Ð SOIC Packages: ± 7 mW/ _C from 65_ to 125_C TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter		Min	Max	Unit
VCC	DC Supply Voltage		2.0	5.5	V
Vin	DC Input Voltage		0	5.5	V
Vout	DC Output Voltage		0	VCC	V
TA	Operating Temperature		± 40	+ 85	_C
tr, tf	Input Rise and Fall Time	VCC = 3.3V ±0.3V	0	100	ns/V
		VCC =5.0V ±0.5V	0	20

DC ELECTRICAL CHARACTERISTICS

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

				VCC		TA = 25°C		TA = ± 40 to 85°C
	Symbol	Parameter	Test Conditions	V	Min	Typ	Max	Min	Max	Unit
	VIH	Minimum High±Level		2.0	1.50			1.50		V
		Input Voltage		3.0 to	VCC x 0.7			VCC x 0.7
				5.5
	VIL	Maximum Low±Level		2.0			0.50		0.50	V
		Input Voltage		3.0 to			VCC x 0.3		VCC x 0.3
				5.5
	VOH	Minimum High±Level	Vin = VIH or VIL	2.0	1.9	2.0		1.9		V
		Output Voltage	IOH = ± 50μA	3.0	2.9	3.0		2.9
				4.5	4.4	4.5		4.4
			Vin = VIH or VIL
			IOH = ± 4mA	3.0	2.58			2.48
			IOH = ± 8mA	4.5	3.94			3.80
	VOL	Maximum Low±Level	Vin = VIH or VIL	2.0		0.0	0.1		0.1	V
		Output Voltage	IOL = 50μA	3.0		0.0	0.1		0.1
				4.5		0.0	0.1		0.1
			Vin = VIH or VIL
			IOL = 4mA	3.0			0.36		0.44
			IOL = 8mA	4.5			0.36		0.44
	Iin	Maximum Input	Vin = 5.5 V or GND	0 to 5.5			± 0.1		± 1.0	μA
		Leakage Current	(DIR, OE)
	MOTOROLA			2			VHC Data ± Advanced CMOS Logic
									DL203 Ð Rev 1

MC74VHC245

DC ELECTRICAL CHARACTERISTICS

			VCC		TA = 25°C		TA = ± 40 to 85°C
Symbol	Parameter	Test Conditions	V	Min	Typ	Max	Min	Max	Unit
IOZ	Maximum Three±State	Vin = VIL or VIH	5.5			± 0.25		± 2.5	μA
	Leakage Current	Vout = VCC or GND
ICC	Maximum Quiescent	Vin = VCC or GND	5.5			4.0		40.0	μA
	Supply Current

AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)

						TA = 25°C				TA = ± 40 to 85°C
Symbol		Parameter	Test Conditions		Min	Typ		Max		Min	Max		Unit
tPLH,		Maximum Propagation Delay,	VCC = 3.3 ± 0.3V	CL = 15pF		5.8		8.4		1.0	10.0		ns
tPHL		A to B or B to A		CL = 50pF		8.3		11.9		1.0	13.5
			VCC = 5.0 ± 0.5V	CL = 15pF		4.0		5.5		1.0	6.5
				CL = 50pF		5.5		7.5		1.0	8.5
tPZL,		Output Enable Time	VCC = 3.3 ± 0.3V	CL = 15pF		8.5		13.2		1.0	15.5		ns
tPZH		OE to A or B	RL = 1 kΩ	CL = 50pF		11.0		16.7		1.0	19.0
			VCC = 5.0 ± 0.5V	CL = 15pF		5.8		8.5		1.0	10.0
			RL = 1 kΩ	CL = 50pF		7.3		10.6		1.0	12.0
tPLZ,		Output Disable Time	VCC = 3.3 ± 0.3V	CL = 50pF		11.5		15.8		1.0	18.0		ns
tPHZ		OE to A or B	RL = 1 kΩ
			VCC = 5.0 ± 0.5V	CL = 50pF		7.0		9.7		1.0	11.0
			RL = 1 kΩ
tOSLH,		Output to Output Skew	VCC = 3.3 ± 0.3V	CL = 50pF				1.5			1.5		pF
tOSHL			(Note 1.)
			VCC = 5.0 ± 0.5V	CL = 50pF				1.0			1.0		ns
			(Note 1.)
Cin		Maximum Input Capacitance				4		10			10		pF
		DIR, OE
CI/O		Maximum Three±State				8							pF
		I/O Capacitance
							Typical @ 25°C, VCC = 5.0V
CPD		Power Dissipation Capacitance (Note 2.)							21				pF

1.Parameter guaranteed by design. tOSLH = |tPLHm ± tPLHn|, tOSHL = |tPHLm ± tPHLn|.

2.CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.

Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 8 (per bit). CPD is used to determine the no±load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.

NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V)

		TA = 25°C
Symbol	Parameter	Typ	Max	Unit
VOLP	Quiet Output Maximum Dynamic VOL	0.9	1.2	V
VOLV	Quiet Output Minimum Dynamic VOL	±0.9	±1.2	V
VIHD	Minimum High Level Dynamic Input Voltage		3.5	V
VILD	Maximum Low Level Dynamic Input Voltage		1.5	V

VHC Data ± Advanced CMOS Logic	3	MOTOROLA
DL203 Ð Rev 1