MC74LVX8053
Analog Multiplexer /
Demultiplexer
High±Performance Silicon±Gate CMOS
The MC74LVX8053 utilizes silicon±gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. This analog multiplexer/demultiplexer controls analog voltages that may vary across the complete power supply range (from VCC to GND).
The LVX8053 is similar in pinout to the high±speed HC4053A, and the metal±gate MC14053B. The Channel±Select inputs determine which one of the Analog Inputs/Outputs is to be connected, by means of an analog switch, to the Common Output/Input. When the Enable pin is HIGH, all analog switches are turned off.
The Channel±Select and Enable inputs are compatible with standard CMOS outputs; with pull±up resistors they are compatible with LSTTL outputs.
This device has been designed so that the ON resistance (Ron) is more linear over input voltage than Ron of metal±gate CMOS analog switches.
•Fast Switching and Propagation Speeds
•Low Crosstalk Between Switches
•Diode Protection on All Inputs/Outputs
•Analog Power Supply Range (VCC ± GND) = 2.0 to 6.0 V
•Digital (Control) Power Supply Range (VCC ± GND) = 2.0 to 6.0 V
•Improved Linearity and Lower ON Resistance Than Metal±Gate Counterparts
•Low Noise
•In Compliance With the Requirements of JEDEC Standard No. 7A
•Chip Complexity: LVX8053 Ð 156 FETs or 39 Equivalent Gates
LOGIC DIAGRAM
Triple Single±Pole, Double±Position Plus Common Off
|
X0 |
12 |
X SWITCH |
14 |
X |
|
|
X1 |
13 |
|
|
|
|
ANALOG |
Y0 |
2 |
Y SWITCH |
15 |
Y |
COMMON |
Y1 |
1 |
|
OUTPUTS/INPUTS |
|||
INPUTS/OUTPUTS |
|
|
|
|
||
|
Z0 |
5 |
|
4 |
|
|
|
3 |
Z SWITCH |
Z |
|
||
|
Z1 |
|
|
|
|
|
|
A 11 |
|
|
|
|
|
CHANNEL-SELECT |
B |
10 |
|
PIN 16 = VCC |
||
INPUTS |
C |
9 |
|
PIN 8 = GND |
|
|
|
|
|
|
|
||
ENABLE |
6 |
|
|
|
|
|
NOTE: This device allows independent control of each switch.
Channel±Select Input A controls the X±Switch, Input B controls the Y±Switch and Input C controls the Z±Switch
http://onsemi.com
16±LEAD SOIC |
16±LEAD TSSOP |
D SUFFIX |
DT SUFFIX |
CASE 751B |
CASE 948F |
PIN CONNECTION AND
MARKING DIAGRAM (Top View)
VCC |
Y |
|
X |
|
X1 |
|
X0 |
|
A |
|
B |
|
C |
|
16 |
|
15 |
|
14 |
|
13 |
|
12 |
|
11 |
|
10 |
|
9 |
1 |
|
2 |
|
3 |
|
4 |
|
5 |
|
6 |
|
7 |
|
8 |
Y1 |
Y0 |
|
Z1 |
|
Z |
|
Z0 |
Enable |
NC |
GND |
||||
For detailed package marking information, see the Marking Diagram section on page 11 of this data sheet.
FUNCTION TABLE ± MC74LVX8053
Control Inputs |
|
|
|
|
||
|
|
|
|
|
|
|
|
|
Select |
|
|
|
|
Enable |
C |
B |
A |
ON Channels |
||
L |
L |
L |
L |
Z0 |
Y0 |
X0 |
L |
L |
L |
H |
Z0 |
Y0 |
X1 |
L |
L |
H |
L |
Z0 |
Y1 |
X0 |
L |
L |
H |
H |
Z0 |
Y1 |
X1 |
L |
H |
L |
L |
Z1 |
Y0 |
X0 |
L |
H |
L |
H |
Z1 |
Y0 |
X1 |
L |
H |
H |
L |
Z1 |
Y1 |
X0 |
L |
H |
H |
H |
Z1 |
Y1 |
X1 |
H |
X |
X |
X |
|
NONE |
|
|
|
|
|
|
|
|
X = Don't Care
ORDERING INFORMATION
Device |
Package |
Shipping |
|
|
|
MC74LVX8053D |
SOIC |
48 Units/Rail |
|
|
|
MC74LVX8053DR2 |
SOIC |
2500 Units/Reel |
|
|
|
MC74LVX8053DT |
TSSOP |
96 Units/Rail |
|
|
|
MC74LVX8053DTR2 |
TSSOP |
2500 Units/Reel |
|
|
|
Semiconductor Components Industries, LLC, 1999 |
1 |
Publication Order Number: |
March, 2000 ± Rev. 2 |
|
MC74LVX8053/D |
|
|
MC74LVX8053 |
|
||
MAXIMUM RATINGS* |
|
|
|
||
|
|
|
|
||
Symbol |
Parameter |
Value |
Unit |
||
|
|
|
|
|
|
VCC |
Positive DC Supply Voltage |
(Referenced to GND) |
± 0.5 to + 7.0 |
V |
|
VIS |
Analog Input Voltage |
|
± 0.5 to VCC + 0.5 |
V |
|
Vin |
Digital Input Voltage (Referenced to GND) |
± 0.5 to VCC + 0.5 |
V |
||
I |
DC Current, Into or Out of Any Pin |
± 20 |
mA |
||
|
|
|
|
|
|
PD |
Power Dissipation in Still Air, |
SOIC Package² |
500 |
mW |
|
|
|
TSSOP Package² |
450 |
|
|
|
|
|
|
|
|
Tstg |
Storage Temperature Range |
|
± 65 to + 150 |
_C |
|
TL |
Lead Temperature, 1 mm from Case for 10 Seconds |
260 |
_C |
||
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.
²Derating Ð SOIC Package: ± 7 mW/ _C from 65_ to 125_C TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol |
Parameter |
|
Min |
Max |
Unit |
|
|
|
|
|
|
VCC |
Positive DC Supply Voltage |
(Referenced to GND) |
2.0 |
6.0 |
V |
VIS |
Analog Input Voltage |
|
0.0 |
VCC |
V |
Vin |
Digital Input Voltage (Referenced to GND) |
GND |
VCC |
V |
|
VIO* |
Static or Dynamic Voltage Across Switch |
|
1.2 |
V |
|
TA |
Operating Temperature Range, All Package Types |
± 55 |
+ 85 |
_C |
|
tr, tf |
Input Rise/Fall Time |
|
|
|
ns/V |
|
(Channel Select or Enable Inputs) |
|
|
|
|
|
|
VCC = 3.3 V ± 0.3 V |
0 |
100 |
|
|
|
VCC = 5.0 V ± 0.5 V |
0 |
20 |
|
*For voltage drops across switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC. Unused inputs must always be
tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
http://onsemi.com
2
MC74LVX8053
DC CHARACTERISTICS Ð Digital Section (Voltages Referenced to GND)
|
|
|
VCC |
Guaranteed Limit |
|
|
||
|
|
|
|
|
|
|
|
|
Symbol |
Parameter |
Condition |
V |
±55 to 25°C |
≤85°C |
≤125°C |
Unit |
|
|
|
|
|
|
|
|
|
|
VIH |
Minimum High±Level Input |
Ron = Per Spec |
2.0 |
1.50 |
1.50 |
|
1.50 |
V |
|
Voltage, Channel±Select or |
|
3.0 |
2.10 |
2.10 |
|
2.10 |
|
|
Enable Inputs |
|
4.5 |
3.15 |
3.15 |
|
3.15 |
|
|
|
|
5.5 |
3.85 |
3.85 |
|
3.85 |
|
|
|
|
|
|
|
|
|
|
VIL |
Maximum Low±Level Input |
Ron = Per Spec |
2.0 |
0.5 |
0.5 |
|
0.5 |
V |
|
Voltage, Channel±Select or |
|
3.0 |
0.9 |
0.9 |
|
0.9 |
|
|
Enable Inputs |
|
4.5 |
1.35 |
1.35 |
|
1.35 |
|
|
|
|
5.5 |
1.65 |
1.65 |
|
1.65 |
|
|
|
|
|
|
|
|
|
|
Iin |
Maximum Input Leakage Current, |
Vin = VCC or GND, |
5.5 |
± 0.1 |
± 1.0 |
|
± 1.0 |
μA |
|
Channel±Select or Enable Inputs |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ICC |
Maximum Quiescent Supply |
Channel Select, Enable and |
5.5 |
4 |
40 |
|
160 |
μA |
|
Current (per Package) |
VIS = VCC or GND; VIO = 0 V |
|
|
|
|
|
|
DC ELECTRICAL CHARACTERISTICS Analog Section
|
|
|
|
Guaranteed Limit |
|
|
|
|
|||||
|
|
|
VCC |
|
|
|
|
|
|
|
|
|
|
|
|
|
± 55 to |
v |
|
_ |
|
v |
|
_ |
|
|
|
Symbol |
Parameter |
Test Conditions |
V |
_ |
85 |
C |
125 |
C |
Unit |
||||
|
25 C |
|
|
|
|
||||||||
Ron |
Maximum ªONº Resistance |
Vin = VIL or VIH |
3.0 |
40 |
|
45 |
|
|
|
50 |
|
|
Ω |
|
|
VIS = VCC to GND |
4.5 |
30 |
|
32 |
|
|
|
37 |
|
|
|
|
|
|IS| v 10.0 mA (Figures 1, 2) |
5.5 |
25 |
|
28 |
|
|
|
30 |
|
|
|
|
|
Vin = VIL or VIH |
3.0 |
30 |
|
35 |
|
|
|
40 |
|
|
|
|
|
VIS = VCC or GND (Endpoints) |
4.5 |
25 |
|
28 |
|
|
|
35 |
|
|
|
|
|
|IS| v 10.0 mA (Figures 1, 2) |
5.5 |
20 |
|
25 |
|
|
|
30 |
|
|
|
Ron |
Maximum Difference in ªONº |
Vin = VIL or VIH |
3.0 |
15 |
|
20 |
|
|
|
25 |
|
|
Ω |
|
Resistance Between Any Two |
VIS = 1/2 (VCC ± GND) |
4.5 |
8.0 |
|
12 |
|
|
|
15 |
|
|
|
|
Channels in the Same Package |
|IS| v 10.0 mA |
5.5 |
8.0 |
|
12 |
|
|
|
15 |
|
|
|
Ioff |
Maximum Off±Channel Leakage |
Vin = VIL or VIH; |
5.5 |
0.1 |
|
0.5 |
|
|
1.0 |
|
|
μA |
|
|
Current, Any One Channel |
VIO = VCC or GND; |
|
|
|
|
|
|
|
|
|
|
|
|
|
Switch Off (Figure 3) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Maximum Off±Channel |
Vin = VIL or VIH; |
5.5 |
0.1 |
|
1.0 |
|
|
2.0 |
|
|
|
|
|
Leakage Current, |
VIO = VCC or GND; |
|
|
|
|
|
|
|
|
|
|
|
|
Common Channel |
Switch Off (Figure 4) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Ion |
Maximum On±Channel |
Vin = VIL or VIH; |
5.5 |
0.1 |
|
1.0 |
|
|
2.0 |
|
|
μA |
|
|
Leakage Current, |
Switch±to±Switch = |
|
|
|
|
|
|
|
|
|
|
|
|
Channel±to±Channel |
VCC or GND; (Figure 5) |
|
|
|
|
|
|
|
|
|
|
|
http://onsemi.com
3
MC74LVX8053
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 3 ns)
|
|
|
VCC |
Guaranteed Limit |
|
|
|
||
|
|
|
|
|
|
|
|
|
|
Symbol |
Parameter |
|
V |
±55 to 25°C |
≤85°C |
|
≤125°C |
Unit |
|
|
|
|
|
|
|
|
|
|
|
tPLH, |
Maximum Propagation Delay, Channel±Select to Analog Output |
2.0 |
30 |
35 |
|
|
40 |
ns |
|
tPHL |
(Figure 9) |
|
3.0 |
20 |
25 |
|
|
30 |
|
|
|
|
4.5 |
15 |
18 |
|
|
22 |
|
|
|
|
5.5 |
15 |
18 |
|
|
20 |
|
|
|
|
|
|
|
|
|
|
|
tPLH, |
Maximum Propagation Delay, Analog Input to Analog Output |
2.0 |
4.0 |
6.0 |
|
|
8.0 |
ns |
|
tPHL |
(Figure 10) |
|
3.0 |
3.0 |
5.0 |
|
|
6.0 |
|
|
|
|
4.5 |
1.0 |
2.0 |
|
|
2.0 |
|
|
|
|
5.5 |
1.0 |
2.0 |
|
|
2.0 |
|
|
|
|
|
|
|
|
|
|
|
tPLZ, |
Maximum Propagation Delay, Enable to Analog Output |
2.0 |
30 |
35 |
|
|
40 |
ns |
|
tPHZ |
(Figure 11) |
|
3.0 |
20 |
25 |
|
|
30 |
|
|
|
|
4.5 |
15 |
18 |
|
|
22 |
|
|
|
|
5.5 |
15 |
18 |
|
|
20 |
|
|
|
|
|
|
|
|
|
|
|
tPZL, |
Maximum Propagation Delay, Enable to Analog Output |
2.0 |
20 |
25 |
|
|
30 |
ns |
|
tPZH |
(Figure 11) |
|
3.0 |
12 |
14 |
|
|
15 |
|
|
|
|
4.5 |
8.0 |
10 |
|
|
12 |
|
|
|
|
5.5 |
8.0 |
10 |
|
|
12 |
|
|
|
|
|
|
|
|
|
|
|
Cin |
Maximum Input Capacitance, Channel±Select or Enable Inputs |
|
10 |
10 |
|
|
10 |
pF |
|
CI/O |
Maximum Capacitance |
Analog I/O |
|
35 |
35 |
|
|
35 |
pF |
|
(All Switches Off) |
Common O/I |
|
50 |
50 |
|
|
50 |
|
|
|
|
|
|
|
|
|
|
|
|
|
Feedthrough |
|
1.0 |
1.0 |
|
|
1.0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
CPD |
|
|
|
Typical @ 25°C, V = 5.0 V |
|
pF |
|||
|
|
|
|
|
CC |
|
|
|
|
|
Power Dissipation Capacitance (Figure 13)* |
|
|
|
45 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
* Used to determine the no±load dynamic power consumption: PD = CPD VCC2f + ICC VCC.
http://onsemi.com
4
Loading...