MOTOROLA MC74VHC393ML1, MC74VHC393ML2, MC74VHC393M, MC74VHC393MEL, MC74VHC393D Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Dual 4-Bit Binary Ripple

Counter

The MC74VHC393 is an advanced high speed CMOS dual 4±bit binary ripple counter fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.

This device consists of two independent 4±bit binary ripple counters with parallel outputs from each counter stage. A 256 counter can be obtained by cascading the two binary counters.

Internal flip±flops are triggered by high±to±low transitions of the clock input. Reset for the counters is asynchronous and active±high. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used as clocks or as strobes except when gated with the Clock of the VHC393.

The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems.

•High Speed: fmax = 170MHz (Typ) at VCC = 5V

•Low Power Dissipation: ICC = 4μA (Max) at TA = 25°C

•High Noise Immunity: VNIH = VNIL = 28% VCC

•Power Down Protection Provided on Inputs

•Balanced Propagation Delays

•Designed for 2V to 5.5V Operating Range

•Low Noise: VOLP = 0.8V (Max)

•Pin and Function Compatible with Other Standard Logic Families

•Latchup Performance Exceeds 300mA

•ESD Performance: HBM > 2000V; Machine Model > 200V

•Chip Complexity: 236 FETs or 59 Equivalent Gates

LOGIC DIAGRAM

					BINARY		3, 11	nQA
							4, 10
		1, 13			COUNTER			nQB
CPn							5, 9
								nQC
							6, 8
								nQD
RDn		2, 12

FUNCTION TABLE

Inputs
Clock	Reset	Outputs
X	H	L
H	L	No Change
L	L	No Change
↑	L	No Change
↓	L	Next State

MC74VHC393

D SUFFIX

14±LEAD SOIC PACKAGE

CASE 751A±03

DT SUFFIX

14±LEAD TSSOP PACKAGE

CASE 948G±01

M SUFFIX

14±LEAD SOIC EIAJ PACKAGE

CASE 965±01

ORDERING INFORMATION

MC74VHCXXXD SOIC MC74VHCXXXDT TSSOP MC74VHCXXXM SOIC EIAJ

PIN ASSIGNMENT

	CP1		1	14		VCC
RD1			2	13		CP2
1QA			3	12		RD2
1QB			4	11		2QA
1QC			5	10		2QB
1QD			6	9		2QC
GND			7	8		2QD

6/97

Motorola, Inc. 1997

1

REV 0

MC74VHC393

MAXIMUM RATINGS*

Symbol	Parameter		Value	Unit
VCC	DC Supply Voltage		± 0.5 to + 7.0	V
Vin	DC Input Voltage		± 0.5 to + 7.0	V
Vout	DC Output Voltage		± 0.5 to VCC + 0.5	V
IIK	Input Diode Current		± 20	mA
IOK	Output Diode Current		± 20	mA
Iout	DC Output Current, per Pin		± 25	mA
ICC	DC Supply Current, VCC and GND Pins		± 75	mA
PD	Power Dissipation in Still Air,	SOIC Packages²	500	mW
		TSSOP Package²	450
Tstg	Storage Temperature		± 65 to + 150	_C

*Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute±maximum±rated conditions is not implied.

²Derating Ð SOIC Packages: ± 7 mW/ _C from 65_ to 125_C TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter		Min	Max	Unit
VCC	DC Supply Voltage		2.0	5.5	V
Vin	DC Input Voltage		0	5.5	V
Vout	DC Output Voltage		0	VCC	V
TA	Operating Temperature		± 40	+ 85	_C
tr, tf	Input Rise and Fall Time	VCC = 3.3V	0	100	ns/V
		VCC = 5.0V	0	20

DC ELECTRICAL CHARACTERISTICS

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

			VCC		TA = 25°C		TA = ± 40 to 85°C
Symbol	Parameter	Test Conditions	V	Min	Typ	Max	Min	Max	Unit
VIH	Minimum High±Level		2.0	1.50			1.50		V
	Input Voltage		3.0 to	VCC x 0.7			VCC x 0.7
			5.5
VIL	Maximum Low±Level		2.0			0.50		0.50	V
	Input Voltage		3.0 to			VCC x 0.3		VCC x 0.3
			5.5
VOH	Minimum High±Level	Vin = VIH or VIL	2.0	1.9	2.0		1.9		V
	Output Voltage	IOH = ± 50μA	3.0	2.9	3.0		2.9
			4.5	4.4	4.5		4.4
		Vin = VIH or VIL
		IOH = ± 4mA	3.0	2.58			2.48
		IOH = ± 8mA	4.5	3.94			3.80
VOL	Maximum Low±Level	Vin = VIH or VIL	2.0		0.0	0.1		0.1	V
	Output Voltage	IOL = 50μA	3.0		0.0	0.1		0.1
			4.5		0.0	0.1		0.1
		Vin = VIH or VIL
		IOL = 4mA	3.0			0.36		0.44
		IOL = 8mA	4.5			0.36		0.44

MOTOROLA	2	VHC Data ± Advanced CMOS Logic
		DL203 Ð Rev 1

MC74VHC393

DC ELECTRICAL CHARACTERISTICS

			VCC		TA = 25°C		TA = ± 40 to 85°C
Symbol	Parameter	Test Conditions	V	Min	Typ	Max	Min	Max	Unit
Iin	Maximum Input	Vin = 5.5V or GND	0 to 5.5			± 0.1		± 1.0	μA
	Leakage Current
ICC	Maximum Quiescent	Vin = VCC or GND	5.5			4.0		40.0	μA
	Supply Current

AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)

						TA = 25°C				TA = ± 40 to 85°C
Symbol		Parameter	Test Conditions		Min	Typ		Max		Min	Max		Unit
fmax		Maximum Clock Frequency	VCC = 3.3 ± 0.3V	CL = 15pF	75	120				65			ns
		(50% Duty Cycle)		CL = 50pF	45	65				35
			VCC = 5.0 ± 0.5V	CL = 15pF	125	170				105
				CL = 50pF	85	115				75
tPLH,		Maximum Propagation Delay,	VCC = 3.3 ± 0.3V	CL = 15pF		8.6		13.2		1.0	15.5		ns
tPHL		CP to QA		CL = 50pF		11.1		16.7		1.0	19.0
			VCC = 5.0 ± 0.5V	CL = 15pF		5.8		8.5		1.0	10.0
				CL = 50pF		7.3		10.5		1.0	12.0
tPLH,		Maximum Propagation Delay,	VCC = 3.3 ± 0.3V	CL = 15pF		10.2		15.8		1.0	18.5		ns
tPHL		CP to QB		CL = 50pF		12.7		19.3		1.0	22.0
			VCC = 5.0 ± 0.5V	CL = 15pF		6.8		9.8		1.0	11.5
				CL = 50pF		8.3		11.8		1.0	13.5
tPLH,		Maximum Propagation Delay,	VCC = 3.3 ± 0.3V	CL = 15pF		11.7		18.0		1.0	21.0		ns
tPHL		CP to QC		CL = 50pF		14.2		21.5		1.0	24.5
			VCC = 5.0 ± 0.5V	CL = 15pF		7.7		11.2		1.0	13.0
				CL = 50pF		9.2		13.2		1.0	15.0
tPLH,		Maximum Propagation Delay,	VCC = 3.3 ± 0.3V	CL = 15pF		13.0		19.7		1.0	23.0		ns
tPHL		CP to QD		CL = 50pF		15.5		23.2		1.0	26.5
			VCC = 5.0 ± 0.5V	CL = 15pF		8.5		12.5		1.0	14.5
				CL = 50pF		10.0		14.5		1.0	16.5
tPHL		Maximum Propagation Delay,	VCC = 3.3 ± 0.3V	CL = 15pF		7.9		12.3		1.0	14.5		ns
		RD to Qn		CL = 50pF		10.4		15.8		1.0	18.0
			VCC = 5.0 ± 0.5V	CL = 15pF		5.4		8.1		1.0	9.5
				CL = 50pF		6.9		10.1		1.0	11.5
tOSLH,		Output to Output Skew	VCC = 3.3 ± 0.3V	CL = 50pF				1.5			1.5		pF
tOSHL			(Note NO TAG)
			VCC = 5.0 ± 0.5V	CL = 50pF				1.0			1.0		pF
			(Note NO TAG)
Cin		Maximum Input Capacitance				4		10			10		pF
							Typical @ 25°C, VCC = 5.0V
CPD		Power Dissipation Capacitance (Note NO TAG)							23				pF

1.Parameter guaranteed by design. tOSLH = |tPLHm ± tPLHn|, tOSHL = |tPHLm ± tPHLn|.

2.CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.

Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 2 (per 4±bit counter). CPD is used to determine the no±load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.

VHC Data ± Advanced CMOS Logic	3	MOTOROLA
DL203 Ð Rev 1