MOTOROLA MC74VHC138MEL, MC74VHC138ML1, MC74VHC138ML2, MC74VHC138N, MC74VHC138DTEL Datasheet

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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

3-to-8 Line Decoder

The MC74VHC138 is an advanced high speed CMOS 3±to±8 decoder fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.

When the device is enabled, three Binary Select inputs (A0 ± A2) determine which one of the outputs (Y0 ± Y7) will go Low. When enable input E3 is held Low or either E2 or E1 is held High, decoding function is inhibited and all outputs go high. E3, E2, and E1 inputs are provided to ease cascade connection and for use as an address decoder for memory systems.

The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems.

•High Speed: tPD = 5.7ns (Typ) at VCC = 5V

•Low Power Dissipation: ICC = 4μA (Max) at TA = 25°C

•High Noise Immunity: VNIH = VNIL = 28% VCC

•Power Down Protection Provided on Inputs

•Balanced Propagation Delays

•Designed for 2V to 5.5V Operating Range

•Low Noise: VOLP = 0.8 V (Max)

•Pin and Function Compatible with Other Standard Logic Families

•Latchup Performance Exceeds 300mA

•ESD Performance: HBM > 2000V; Machine Model > 200V

•Chip Complexity: 122 FETs or 30.5 Equivalent Gates

FUNCTION TABLE

Inputs

Outputs

A2 A1 A0

X X H

X X X

H H H H H H H H

X H X

X X X

H H H H H H H H

L X X

X X X

H H H H H H H H

H L L

L L L

L H H H H H H H

H L L

L L H

H L H H H H H H

H L L

L H L

H H L H H H H H

H L L

L H H

H H H L H H H H

H L L

H H H H L H H H

H L L

H L H

H H H H H L H H

H L L

H H L

H H H H H H L H

H L L

H H H

H H H H H H H L

H = high level (steady state); L = low level (steady state);

X = don't care

SELECT

INPUTS

ACTIVE±LOW

OUTPUTS

MC74VHC138

D SUFFIX

16±LEAD SOIC PACKAGE

CASE 751B±05

DT SUFFIX

16±LEAD TSSOP PACKAGE

CASE 948F±01

M SUFFIX

16±LEAD SOIC EIAJ PACKAGE

CASE 966±01

ORDERING INFORMATION

MC74VHCXXXD SOIC MC74VHCXXXDT TSSOP MC74VHCXXXM SOIC EIAJ

PIN ASSIGNMENT

	A0	1	16	VCC


	A1	2	15
				Y0



	A2	3	14	Y1



	E1	4	13	Y2

		5	12
	E2			Y3


		6	11
	E3			Y4

		7	10
	Y7			Y5



GND		8	9	Y6

ENABLE	E3	6
		5	LOGIC DIAGRAM
INPUTS	E2
		4
	E1

6/97
Motorola, Inc. 1997			1	REV 1

MC74VHC138

		EXPANDED LOGIC DIAGRAM
		15	Y0
		14	Y1
A0	1	13	Y2
A1	2	12	Y3
	3	11	Y4
A2	3
		10	Y5
E2	5
E1	4	9	Y6
			Y6
		7	Y7
E3	6

MOTOROLA	2	VHC Data ± Advanced CMOS Logic
		DL203 Ð Rev 1

MC74VHC138

MAXIMUM RATINGS*

Symbol	Parameter		Value	Unit

VCC	DC Supply Voltage		± 0.5 to + 7.0	V
Vin	DC Input Voltage		± 0.5 to + 7.0	V
Vin	DC Input Voltage		± 0.5 to + 7.0	V
Vout	DC Output Voltage		± 0.5 to VCC + 0.5	V
IIK	Input Diode Current		± 20	mA
IOK	Output Diode Current		± 20	mA
Iout	DC Output Current, per Pin		± 25	mA
ICC	DC Supply Current, VCC and GND Pins		± 75	mA
PD	Power Dissipation in Still Air,	SOIC Packages²	500	mW
		TSSOP Package²	450

Tstg	Storage Temperature		± 65 to + 150	_C

*Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute±maximum±rated conditions is not implied.

²Derating Ð SOIC Packages: ± 7 mW/ _C from 65_ to 125_C TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter		Min	Max	Unit

VCC	DC Supply Voltage		2.0	5.5	V
Vin	DC Input Voltage		0	5.5	V
Vout	DC Output Voltage		0	VCC	V
TA	Operating Temperature		± 40	+ 85	_C
tr, tf	Input Rise and Fall Time	VCC = 3.3V ±0.3V	0	100	ns/V
		VCC =5.0V ±0.5V	0	20

DC ELECTRICAL CHARACTERISTICS

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

			VCC		TA = 25°C		TA = ± 40 to 85°C
Symbol	Parameter	Test Conditions	V	Min	Typ	Max	Min	Max	Unit

VIH	Minimum High±Level		2.0	1.50			1.50		V
	Input Voltage		3.0 to	VCC x 0.7			VCC x 0.7
			5.5

VIL	Maximum Low±Level		2.0			0.50		0.50	V
	Input Voltage		3.0 to			VCC x 0.3		VCC x 0.3
			5.5

VOH	Minimum High±Level	Vin = VIH or VIL	2.0	1.9	2.0		1.9		V
	Output Voltage	IOH = ± 50μA	3.0	2.9	3.0		2.9
			4.5	4.4	4.5		4.4

		Vin = VIH or VIL
		IOH = ± 4mA	3.0	2.58			2.48
		IOH = ± 8mA	4.5	3.94			3.80
VOL	Maximum Low±Level	Vin = VIH or VIL	2.0		0.0	0.1		0.1	V
	Output Voltage	IOL = 50μA	3.0		0.0	0.1		0.1
			4.5		0.0	0.1		0.1

		Vin = VIH or VIL
		IOL = 4mA	3.0			0.36		0.44
		IOL = 8mA	4.5			0.36		0.44

VHC Data ± Advanced CMOS Logic	3	MOTOROLA
DL203 Ð Rev 1

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