MOTOROLA MC74VHC157MEL, MC74VHC157ML1, MC74VHC157DTR2, MC74VHC157D, MC74VHC157DR2 Datasheet

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MOTOROLA MC74VHC157MEL, MC74VHC157ML1, MC74VHC157DTR2, MC74VHC157D, MC74VHC157DR2 Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Quad 2-Channel Multiplexer

The MC74VHC157 is an advanced high speed CMOS quad 2±channel multiplexer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.

It consists of four 2±input digital multiplexers with common select (S) and enable (E) inputs. When E is held High, selection of data is inhibited and all the outputs go Low.

The select decoding determines whether the A or B inputs get routed to the corresponding Y outputs.

The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems.

High Speed: tPD = 4.1ns (Typ) at VCC = 5V

Low Power Dissipation: ICC = 4μA (Max) at TA = 25°C

High Noise Immunity: VNIH = VNIL = 28% VCC

Power Down Protection Provided on Inputs

Balanced Propagation Delays

Designed for 2V to 5.5V Operating Range

Low Noise: VOLP = 0.8V (Max)

Pin and Function Compatible with Other Standard Logic Families

Latchup Performance Exceeds 300mA

ESD Performance: HBM > 2000V; Machine Model > 200V

Chip Complexity: 82 FETs or 20 Equivalent Gates

 

 

EXPANDED LOGIC DIAGRAM

 

 

2

 

 

 

A0

4

 

 

3

Y0

 

 

 

B0

 

 

 

5

 

 

 

A1

 

 

 

6

7

Y1

 

 

 

B1

 

 

NIBBLE

11

 

DATA

INPUTS

 

 

 

A2

 

OUTPUTS

 

 

 

10

9

Y2

 

 

 

B2

 

 

 

14

 

 

 

A3

 

 

 

13

12

Y3

 

B3

 

 

E

15

 

 

1

 

 

S

 

 

 

 

 

FUNCTION TABLE

 

Inputs

Outputs

 

 

 

E

 

S

Y0 ± Y3

H

 

X

 

L

L

 

L

A0

± A3

L

 

H

B0

± B3

MC74VHC157

D SUFFIX

16±LEAD SOIC PACKAGE

CASE 751B±05

DT SUFFIX

16±LEAD TSSOP PACKAGE

CASE 948F±01

M SUFFIX

16±LEAD SOIC EIAJ PACKAGE

CASE 966±01

ORDERING INFORMATION

MC74VHCXXXD SOIC MC74VHCXXXDT TSSOP MC74VHCXXXM SOIC EIAJ

PIN ASSIGNMENT

S

 

1

16

 

VCC

 

 

 

A0

 

 

 

 

 

 

 

2

15

 

E

 

B0

 

3

14

 

A3

 

Y0

 

4

13

 

B3

 

A1

 

5

12

 

Y3

 

B1

 

6

11

 

A2

 

 

 

7

10

 

B2

Y1

 

GND

 

8

9

 

Y2

 

 

 

 

 

 

 

 

 

A0 ± A3, B0 ± B3 = the levels of the respective Data±Word Inputs.

6/97

Motorola, Inc. 1997

1

REV 1

MC74VHC157

MAXIMUM RATINGS*

Symbol

Parameter

 

Value

Unit

 

 

 

 

 

VCC

DC Supply Voltage

 

± 0.5 to + 7.0

V

Vin

DC Input Voltage

 

± 0.5 to + 7.0

V

 

Vout

DC Output Voltage

 

± 0.5 to VCC + 0.5

V

IIK

Input Diode Current

 

± 20

mA

IOK

Output Diode Current

 

± 20

mA

Iout

DC Output Current, per Pin

 

± 25

mA

ICC

DC Supply Current, VCC and GND Pins

± 50

mA

PD

Power Dissipation in Still Air,

SOIC Packages²

500

mW

 

 

TSSOP Package²

450

 

 

 

 

 

 

Tstg

Storage Temperature

 

± 65 to + 150

_C

*Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute±maximum±rated conditions is not implied.

²Derating Ð SOIC Packages: ± 7 mW/ _C from 65_ to 125_C TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

 

Min

Max

Unit

 

 

 

 

 

 

VCC

DC Supply Voltage

 

2.0

5.5

V

Vin

DC Input Voltage

 

0

5.5

V

Vout

DC Output Voltage

 

0

VCC

V

TA

Operating Temperature

 

± 40

+ 85

_C

tr, tf

Input Rise and Fall Time

VCC = 3.3V

0

100

ns/V

 

 

VCC = 5.0V

0

20

 

DC ELECTRICAL CHARACTERISTICS

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

 

 

 

VCC

 

TA = 25°C

 

TA = ± 40 to 85°C

 

Symbol

Parameter

Test Conditions

V

Min

Typ

Max

Min

Max

Unit

 

 

 

 

 

 

 

 

 

 

VIH

Minimum High±Level

 

2.0

1.50

 

 

1.50

 

V

 

Input Voltage

 

3.0 to

VCC x 0.7

 

 

VCC x 0.7

 

 

 

 

 

5.5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VIL

Maximum Low±Level

 

2.0

 

 

0.50

 

0.50

V

 

Input Voltage

 

3.0 to

 

 

VCC x 0.3

 

VCC x 0.3

 

 

 

 

5.5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VOH

Minimum High±Level

Vin = VIH or VIL

2.0

1.9

2.0

 

1.9

 

V

 

Output Voltage

IOH = ± 50μA

3.0

2.9

3.0

 

2.9

 

 

 

 

 

4.5

4.4

4.5

 

4.4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Vin = VIH or VIL

 

 

 

 

 

 

 

 

 

IOH = ± 4mA

3.0

2.58

 

 

2.48

 

 

 

 

IOH = ± 8mA

4.5

3.94

 

 

3.80

 

 

VOL

Maximum Low±Level

Vin = VIH or VIL

2.0

 

0.0

0.1

 

0.1

V

 

Output Voltage

IOL = 50μA

3.0

 

0.0

0.1

 

0.1

 

 

 

 

4.5

 

0.0

0.1

 

0.1

 

 

 

 

 

 

 

 

 

 

 

 

 

Vin = VIH or VIL

 

 

 

 

 

 

 

 

 

IOL = 4mA

3.0

 

 

0.36

 

0.44

 

 

 

IOL = 8mA

4.5

 

 

0.36

 

0.44

 

MOTOROLA

2

VHC Data ± Advanced CMOS Logic

 

 

DL203 Ð Rev 1

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