MOTOROLA MC74LVX4066DR2, MC74LVX4066DT, MC74LVX4066DTR2, MC74LVX4066D Datasheet

MC74LVX4066

Quad Analog Switch/

Multiplexer/Demultiplexer

High±Performance Silicon±Gate CMOS

The MC74LVX4066 utilizes silicon±gate CMOS technology to

achieve fast propagation delays, low ON			resistances, and low
O F F ± c h a n n e l	l e a k a g e	c u r r e n t .	T h i s	b i l a t e r a l

switch/multiplexer/demultiplexer controls analog and digital voltages that may vary across the full power±supply range (from VCC to GND).

The LVX4066 is identical in pinout to the metal±gate CMOS MC14066 and the high±speed CMOS HC4066A. Each device has four independent switches. The device has been designed so that the ON resistances (RON) are much more linear over input voltage than RON of metal±gate CMOS analog switches.

The ON/OFF control inputs are compatible with standard CMOS outputs; with pull±up resistors, they are compatible with LSTTL outputs.

•Fast Switching and Propagation Speeds

•High ON/OFF Output Voltage Ratio

•Low Crosstalk Between Switches

•Diode Protection on All Inputs/Outputs

•Wide Power±Supply Voltage Range (VCC ± GND) = 2.0 to 6.0 Volts

•Analog Input Voltage Range (VCC ± GND) = 2.0 to 6.0 Volts

•Improved Linearity and Lower ON Resistance over Input Voltage than the MC14016 or MC14066

•Low Noise

•Chip Complexity: 44 FETs or 11 Equivalent Gates

LOGIC DIAGRAM

XA 1 2 YA

13

A ON/OFF CONTROL

X	4	3	Y
B			B
B ON/OFF CONTROL	5		ANALOG
			OUTPUTS/INPUTS
X	8	9	Y
C			C
C ON/OFF CONTROL	6
X	11	10	Y
D			D

12

D ON/OFF CONTROL ANALOG INPUTS/OUTPUTS = XA, XB, XC, XD

PIN 14 = VCC

PIN 7 = GND

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14±LEAD SOIC	14±LEAD TSSOP
D SUFFIX	DT SUFFIX
CASE 751A	CASE 948G

PIN CONNECTION AND

MARKING DIAGRAM (Top View)

	X	1	14	VCC
	A			A ON/OFF
	YA	2	13
				CONTROL
	YB	3	12	D ON/OFF
				CONTROL
	XB	4	11	XD
	B ON/OFF	5	10	YD
	CONTROL
	C ON/OFF	6	9	YC
	CONTROL	7	8	XC
	GND

For detailed package marking information, see the Marking Diagram section on page 10 of this data sheet.

FUNCTION TABLE

On/Off Control	State of
Input	Analog Switch
L	Off
H	On

ORDERING INFORMATION

Device	Package	Shipping
MC74LVX4066D	SOIC	55 Units/Rail
MC74LVX4066DR2	SOIC	2500 Units/Reel
MC74LVX4066DT	TSSOP	96 Units/Rail
MC74LVX4066DTR2	TSSOP	2500 Units/Reel

Semiconductor Components Industries, LLC, 1999	1	Publication Order Number:
March, 2000 ± Rev. 2		MC74LVX4066/D

MC74LVX4066

MAXIMUM RATINGS*

	Symbol	Parameter		Value	Unit
	VCC	Positive DC Supply Voltage (Referenced to GND)		± 0.5 to + 7.0	V
	VIS	Analog Input Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
	Vin	Digital Input Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
	Iin	DC Current Into or Out of ON/OFF Control Pins		± 20	mA
	Is	DC Current Into or Out of Switch Pins		± 20	mA
	PD	Power Dissipation in Still Air,	SOIC Package²	500	mW
			TSSOP Package²	450
	Tstg	Storage Temperature		± 65 to + 150	_C
	TL	Lead Temperature, 1 mm from Case for 10 Seconds		260	_C

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

²Derating Ð SOIC Package: ± 7 mW/ _C from 65_ to 125_C TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C

RECOMMENDED OPERATING CONDITIONS

Symbol		Parameter	Min	Max	Unit
VCC	Positive DC Supply Voltage (Referenced to GND)		2.0	6.0	V
VIS	Analog Input Voltage (Referenced to GND)		GND	VCC	V
Vin	Digital Input Voltage (Referenced to GND)		GND	VCC	V
VIO*	Static or Dynamic Voltage Across Switch		Ð	1.2	V
TA	Operating Temperature, All Package Types		± 55	+ 85	_C
tr, tf	Input Rise and Fall Time, ON/OFF Control				ns/V
	Inputs (Figure 10)	VCC = 3.3 V ± 0.3 V	0	100
		VCC = 5.0 V ± 0.5 V	0	20

*For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.

DC ELECTRICAL CHARACTERISTIC Digital Section (Voltages Referenced to GND)

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus.

				Guaranteed Limit
			VCC
				± 55 to	v _	v		_
Symbol	Parameter	Test Conditions	V	_			125		C	Unit
				25 C	85 C
VIH	Minimum High±Level Voltage	Ron = Per Spec	2.0	1.5	1.5		1.5			V
	ON/OFF Control Inputs		3.0	2.1	2.1		2.1
	(Note 1)		4.5	3.15	3.15		3.15
			5.5	3.85	3.85		3.85
VIL	Maximum Low±Level Voltage	Ron = Per Spec	2.0	0.5	0.5		0.5			V
	ON/OFF Control Inputs		3.0	0.9	0.9		0.9
	(Note 1)		4.5	1.35	1.35		1.35
			5.5	1.65	1.65		1.65
Iin	Maximum Input Leakage Current	Vin = VCC or GND	5.5V	± 0.1	± 1.0	± 1.0				μA
	ON/OFF Control Inputs
ICC	Maximum Quiescent Supply	Vin = VCC or GND	5.5	4.0	40		160			μA
	Current (per Package)	VIO = 0 V

1. Specifications are for design target only. Not final specification limits.

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MC74LVX4066

DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to GND)

				Guaranteed Limit
			VCC
				± 55 to	v _		v		_
Symbol	Parameter	Test Conditions	V	_		C		125		C	Unit
				25 C	85
Ron	Maximum ªONº Resistance	Vin = VIH	2.0²	Ð	Ð			Ð			Ω
		VIS = VCC to GND	3.0	40	45			50
		|IS| v 10 mA (Figures 1, 2)	4.5	25	30			35
			5.5	20	25			30
		Vin = VIH	2.0	Ð	Ð			Ð
		VIS = VCC or GND (Endpoints)	3.0	30	35			40
		|IS| v 10 mA (Figures 1, 2)	4.5	25	30			35
			5.5	20	25			30
Ron	Maximum Difference in ªONº	Vin = VIH	3.0	15	20			25			Ω
	Resistance Between Any Two	VIS = 1/2 (VCC ± GND)	4.5	10	12			15
	Channels in the Same Package	IS v 2.0 mA	5.5	10	12			15
Ioff	Maximum Off±Channel Leakage	Vin = VIL	5.5	0.1	0.5			1.0			μA
	Current, Any One Channel	VIO = VCC or GND
		Switch Off (Figure 3)
Ion	Maximum On±Channel Leakage	Vin = VIH	5.5	0.1	0.5			1.0			μA
	Current, Any One Channel	VIS = VCC or GND
		(Figure 4)

²At supply voltage (V CC) approaching 2 V the analog switch±on resistance becomes extremely non±linear. Therefore, for low±voltage operation, it is recommended that these devices only be used to control digital signals (See Figure 1a).

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, ON/OFF Control Inputs: tr = tf = 6 ns)

				Guaranteed Limit
			VCC
				± 55 to	v _		v		_
Symbol		Parameter	V	_		C		125		C	Unit
				25 C	85
tPLH,	Maximum Propagation Delay, Analog Input to Analog Output		2.0	4.0	6.0			8.0			ns
tPHL	(Figures 8 and 9)		3.0	3.0	5.0			6.0
			4.5	1.0	2.0			2.0
			5.5	1.0	2.0			2.0
tPLZ,	Maximum Propagation Delay, ON/OFF Control to Analog Output		2.0	30	35			40			ns
tPHZ	(Figures 10 and 11)		3.0	20	25			30
			4.5	15	18			22
			5.5	15	18			20
tPZL,	Maximum Propagation Delay, ON/OFF Control to Analog Output		2.0	20	25			30			ns
tPZH	(Figures 10 and 1 1)		3.0	12	14			15
			4.5	8.0	10			12
			5.5	8.0	10			12
C	Maximum Capacitance	ON/OFF Control Input	Ð	10	10			10			pF
		Control Input = GND
		Analog I/O	Ð	35	35			35
		Feedthrough	Ð	1.0	1.0			1.0
				Typical @ 25°C, VCC = 5.0 V
CPD	Power Dissipation Capacitance (Per Switch) (Figure 13)*				15						pF

* Used to determine the no±load dynamic power consumption: PD = CPD VCC2f + ICC VCC.

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MC74LVX4066

ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)

			VCC	Limit*
Symbol	Parameter	Test Conditions	V	25_C	Unit
BW	Maximum On±Channel Bandwidth	fin = 1 MHz Sine Wave	4.5	150	MHz
	or	Adjust fin Voltage to Obtain 0 dBm at VOS	5.5	160
	Minimum Frequency Response	Increase fin Frequency Until dB Meter Reads ± 3 dB
	(Figure 5)	RL = 50 Ω, CL = 10 pF
Ð	Off±Channel Feedthrough Isolation	fin Sine Wave	4.5	± 50	dB
	(Figure 6)	Adjust fin Voltage to Obtain 0 dBm at VIS	5.5	± 50
		fin = 10 kHz, RL = 600 Ω, CL = 50 pF
		fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF	4.5	± 37
			5.5	± 37
Ð	Feedthrough Noise, Control to	Vin v 1 MHz Square Wave (tr = tf = 6 ns)	4.5	100	mVPP
	Switch	Adjust RL at Setup so that IS = 0 A	5.5	200
	(Figure 7)	RL = 600 Ω, CL = 50 pF
		RL = 10 kΩ, CL = 10 pF	4.5	50
			5.5	100
Ð	Crosstalk Between Any Two	fin Sine Wave	4.5	± 70	dB
	Switches	Adjust fin Voltage to Obtain 0 dBm at VIS	5.5	± 70
	(Figure 12)	fin = 10 kHz, RL = 600 Ω, CL = 50 pF
		fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF	4.5	± 80
			5.5	± 80
THD	Total Harmonic Distortion	fin = 1 kHz, RL = 10 kΩ, CL = 50 pF			%
	(Figure 14)	THD = THDMeasured ± THDSource
		VIS = 4.0 VPP sine wave	4.5	0.10
		VIS = 5.0 VPP sine wave	5.5	0.06

*Guaranteed limits not tested. Determined by design and verified by qualification.

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