October 1987
Revised July 1999
CD40174BC • CD40175BC
Hex D-Type Flip-Flop • Quad D-Type Flip-Flop
General Description
The CD40174BC consists of six positive-edge triggered D- type flip-flops; the true outputs from each flip-flop are externally available. The CD40175BC consists of four positiveedge triggered D-type flip-flops; both the true and complement outputs from each flip-flop are externally available.
All flip-flops are controlled by a common clock and a common clear. Information at the D inputs meeting the set-up time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. The clearing operation, enabled by a negative pulse at Clear input, clears all Q outputs to logical “0” and Q s (CD40175BC only) to logical “1”.
All inputs are protected from static discharge by diode clamps to VDD and VSS.
Features
■Wide supply voltage range: 3V to 15V
■High noise immunity: 0.45 VDD (typ.)
■Low power TTL compatibility:
fan out of 2 driving 74L or 1 driving 74 LS
■Equivalent to MC14174B, MC14175B
■Equivalent to MM74C174, MM74C175
Ordering Code:
Order Number |
Package Number |
Package Description |
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CD40174BCM |
M16A |
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body |
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CD40174BCN |
N16E |
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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CD40175BCM |
M16A |
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body |
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CD40175BCN |
N16E |
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignments for DIP and SOIC
CD40174B |
CD40175B |
Top View |
Top View |
Flop-Flip Type-D Quad • Flop-Flip Type-D Hex CD40175BC • CD40174BC
© 1999 Fairchild Semiconductor Corporation |
DS005987 |
www.fairchildsemi.com |
CD40174BC • CD40175BC
Truth Table
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Inputs |
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Outputs |
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Clear |
Clock |
D |
Q |
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Q |
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(Note 1) |
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L |
X |
X |
L |
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H |
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H |
− |
H |
H |
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L |
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H |
− |
L |
L |
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H |
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H |
H |
X |
NC |
NC |
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H |
L |
X |
NC |
NC |
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H = HIGH Level
L = LOW Level
X = Irrelevant
− = Transition from LOW-to-HIGH level NC = No change
Note 1: Q for CD40175B only
www.fairchildsemi.com |
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Storage Temperature Range (T ) |
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−65°C to +150°C |
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Input Voltage (VIN) |
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0V to VDD VDC |
CD40174BC |
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Absolute Maximum Ratings(Note 2) |
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Recommended Operating |
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(Note 3) |
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Conditions (Note 3) |
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DC Supply Voltage (VDD) |
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−0.5V to +18V |
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Input Voltage (V ) |
−0.5V to V |
DD |
+0.5V |
DC |
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DC Supply Voltage (VDD) |
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3V to 15 VDC |
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IN |
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S |
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−40°C to +85°C |
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Power Dissipation (P ) |
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Operating Temperature Range (TA) |
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CD40175BC |
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D |
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Dual-In-Line |
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700 mW |
Note 2: “Absolute Maximum Ratings” are those values beyond which the |
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Small Outline |
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500 mW |
safety of the device cannot be guaranteed. They are not meant to imply |
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that the devices should be operated at these limits. The tables of “Recom- |
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Lead Temperature (TL) |
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mended Operating Conditions” and “Electrical Characteristics” provide con- |
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ditions for actual device operation. |
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(Soldering, 10 seconds) |
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260°C |
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Note 3: VSS = 0V unless otherwise specified. |
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DC Electrical Characteristics (Note 3) |
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CD40174BC/CD40175BC |
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Symbol |
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Parameter |
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Conditions |
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−40°C |
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+25°C |
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+85°C |
Units |
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Min |
Max |
Min |
Typ |
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Max |
Min |
Max |
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IDD |
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Quiescent Device |
VDD = 5V, VIN = VDD or VSS |
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4 |
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4 |
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30 |
μA |
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Current |
VDD = 10V, VIN = VDD or VSS |
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8 |
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8 |
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60 |
μA |
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VDD = 15V, VIN = VDD or VSS |
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16 |
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16 |
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120 |
μA |
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VOL |
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LOW Level |
VDD = 5V |
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0.05 |
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0.05 |
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0.05 |
V |
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Output Voltage |
VDD = 10V |
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0.05 |
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0.05 |
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0.05 |
V |
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VDD = 15V |
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0.05 |
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0.05 |
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0.05 |
V |
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VOH |
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HIGH Level |
VDD = 5V |
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4.95 |
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4.95 |
5 |
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4.95 |
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V |
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Output Voltage |
VDD = 10V |
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9.95 |
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9.95 |
10 |
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9.95 |
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V |
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VDD = 15V |
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14.95 |
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14.95 |
15 |
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14.95 |
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V |
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VIL |
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LOW Level |
VDD = 5V, VO = 0.5V or 4.5V |
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1.5 |
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1.5 |
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1.5 |
V |
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Input Voltage |
VDD = 10V, VO = 1V or 9V |
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3.0 |
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3.0 |
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3.0 |
V |
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VDD = 15V, VO = 1.5V or 13.5V |
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4.0 |
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4.0 |
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4.0 |
V |
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VIH |
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HIGH Level |
VDD = 5V, VO = 0.5V or 4.5V |
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3.5 |
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3.5 |
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3.5 |
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V |
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Input Voltage |
VDD = 10V, VO = 1V or 9V |
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7.0 |
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7.0 |
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7.0 |
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V |
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VDD = 15V, VO = 1.5V or 13.5V |
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11.0 |
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11.0 |
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11.0 |
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V |
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IOL |
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LOW Level Output |
VDD = 5V, VO = 0.4V |
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0.52 |
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0.44 |
0.88 |
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0.36 |
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mA |
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Current (Note 4) |
VDD = 10V, VO = 0.5V |
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1.3 |
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1.1 |
2.25 |
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0.9 |
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mA |
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VDD = 15V, VO = 1.5V |
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3.6 |
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3.0 |
8.8 |
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2.4 |
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mA |
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IOH |
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HIGH Level Output |
VDD = 5V, VO = 4.6V |
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−0.52 |
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−0.44 |
−0.88 |
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−0.36 |
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mA |
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Current (Note 4) |
VDD = 10V, VO = 9.5V |
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−1.3 |
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−1.1 |
−2.25 |
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−0.9 |
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mA |
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VDD = 15V, VO = 13.5V |
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−3.6 |
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−3.0 |
−8.8 |
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−2.4 |
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mA |
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I |
IN |
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Input Current |
V |
DD |
= 15V, V |
IN |
= 0V |
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−0.30 |
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−10−5 |
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−0.30 |
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−1.0 |
μA |
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V |
DD |
= 15V, V |
IN |
= 15V |
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0.30 |
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10−5 |
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0.30 |
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1.0 |
μA |
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Note 4: IOH and IOL are tested one output at a time. |
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3 |
www.fairchildsemi.com |
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