October 1987
Revised January 1999
CD4021BC
8-Stage Static Shift Register
General Description
The CD4021BC is an 8-stage parallel input/serial output shift register. A parallel/serial control input enables individual JAM inputs to each of 8 stages. Q outputs are available from the sixth, seventh, and eighth stages. All outputs have equal source and sink current capabilities and conform to standard “B” series output drive.
When the parallel/serial control input is in the logical “0” state, data is serially shifted into the register synchronously with the positive transition of the clock. When the parallel/ serial control is in the logical “1” state, data is jammed into each stage of the register asynchronously with the clock.
All inputs are protected against static discharge with diodes to VDD and VSS.
Features
■Wide supply voltage range: 3.0V to 15V
■High noise immunity: 0.45 VDD (typ.)
■Low power TTL compatibility:
Fan out of 2 driving 74L or 1 driving 74LS
■5V–10V–15V parametric ratings
■Symmetrical output characteristics
■Maximum input leakage 1 μA at 15V over full temperature range
Ordering Code:
Order Number |
Order Code |
Package Description |
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CD4021BCM |
M16A |
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body |
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CD4021BCN |
N16E |
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram |
Truth Table |
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Pin Assignments for DIP and SOIC |
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CL |
Serial |
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Parallel/ |
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Q1 |
Qn |
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(Note 1) |
Input |
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Serial |
PI 1 |
PI n |
(Internal) |
(Note 2) |
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Control |
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X |
X |
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1 |
0 |
0 |
0 |
0 |
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X |
X |
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1 |
0 |
1 |
0 |
1 |
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X |
X |
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1 |
1 |
0 |
1 |
0 |
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X |
X |
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1 |
1 |
1 |
1 |
1 |
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0 |
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0 |
X |
X |
0 |
Qn−1 |
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1 |
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0 |
X |
X |
1 |
Qn−1 |
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X |
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0 |
X |
X |
Q1 |
Qn |
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X = Don't care case |
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Note 1: Level change |
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Note 2: No change |
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Top View |
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Register Shift Static Stage-8 CD4021BC
© 1999 Fairchild Semiconductor Corporation |
DS005954.prf |
www.fairchildsemi.com |
CD4021BC
Logic Diagram
www.fairchildsemi.com |
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Absolute Maximum Ratings(Note 3) |
Recommended Operating |
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(Note 4) |
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Conditions (Note 4) |
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Supply Voltage (VDD) |
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−0.5V to +18V |
Supply Voltage (VDD) |
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3V to 15V |
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Input Voltage (VIN) |
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−0.5V to VDD +0.5V |
Input Voltage (VIN) |
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0 to VDD |
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Storage Temperature Range (TS) |
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−65°C to +150°C |
Operating Temperature Range (TA) |
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−40°C to +85°C |
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Power Dissipation (PD) |
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CD4021BCN |
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Dual-In-Line |
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700 mW |
Note 3: “Absolute Maximum Ratings” are those values beyond which the |
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Small Outline |
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500 mW |
safety of the device cannot be guaranteed. Except for “Operating Tempera- |
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ture Range” they are not meant to imply that the devices should be oper- |
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Lead Temperature (TL) |
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ated at these |
limits. The table of “Electrical |
Characteristics” |
provides |
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260°C |
conditions for actual device operation. |
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(Soldering, 10 seconds) |
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Note 4: VSS = 0V unless otherwise specified. |
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DC Electrical Characteristics (Note 4) |
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Symbol |
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Parameter |
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Conditions |
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−40°C |
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+25°C |
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+85°C |
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Units |
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Min |
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Max |
Min |
Typ |
Max |
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Min |
Max |
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IDD |
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Quiescent Device |
VDD = 5V, VIN = VDD or VSS |
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20 |
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0.1 |
20 |
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150 |
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μA |
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Current |
VDD = 10V, VIN = VDD or VSS |
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40 |
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0.2 |
40 |
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300 |
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μA |
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VDD = 15V, VIN = VDD or VSS |
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80 |
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0.3 |
80 |
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600 |
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μA |
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VOL |
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LOW Level |
VDD = 5V |
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0.05 |
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0 |
0.05 |
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0.05 |
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V |
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Output Voltage |
VDD = 10V |
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|IO| < 1 μA |
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0.05 |
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0 |
0.05 |
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0.05 |
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V |
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VDD = 15V |
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0.05 |
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0 |
0.05 |
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0.05 |
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V |
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VOH |
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HIGH Level |
VDD = 5V |
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4.95 |
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4.95 |
5 |
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4.95 |
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V |
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Output Voltage |
VDD = 10V |
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|IO|< 1 μA |
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9.95 |
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9.95 |
10 |
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9.95 |
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V |
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VDD = 15V |
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14.95 |
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14.95 |
15 |
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14.95 |
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V |
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VIL |
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LOW Level |
VDD = 5V, VO = 0.5V or 4.5V |
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1.5 |
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2 |
1.5 |
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1.5 |
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V |
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Input Voltage |
VDD = 10V, VO = 1.0V or 9.0V |
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3.0 |
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4 |
3.0 |
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3.0 |
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V |
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VDD = 15V, VO = 1.5V or 13.5V |
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4.0 |
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6 |
4.0 |
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4.0 |
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V |
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VIH |
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HIGH Level |
VDD = 5V, VO = 0.5V or 4.5V |
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3.5 |
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3.5 |
3 |
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3.5 |
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V |
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Input Voltage |
VDD = 10V, VO = 1.0V or 9.0V |
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7.0 |
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7.0 |
6 |
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7.0 |
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V |
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VDD = 15V, VO = 1.5V or 13.5V |
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11.0 |
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11.0 |
9 |
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11.0 |
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V |
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IOL |
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LOW Level Output |
VDD = 5V, VO = 0.4V |
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0.52 |
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0.44 |
0.88 |
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0.36 |
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mA |
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Current (Note 5) |
VDD = 10V, VO = 0.5V |
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1.3 |
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1.1 |
2.2 |
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0.90 |
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mA |
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VDD = 15V, VO = 1.5V |
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3.6 |
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3.0 |
8 |
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2.4 |
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mA |
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IOH |
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HIGH Level Output |
VDD = 5V, VO = 4.6V |
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−0.52 |
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−0.44 |
−0.88 |
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−0.36 |
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mA |
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Current (Note 5) |
VDD = 10V, VO = 9.5V |
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−1.3 |
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−1.1 |
−2.2 |
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−0.90 |
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mA |
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VDD = 15V, VO = 13.5V |
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−3.6 |
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−3.0 |
−8 |
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−2.4 |
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mA |
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I |
IN |
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Input Current |
V |
DD |
= 15V, V |
IN |
= 0V |
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−0.3 |
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−10−5 |
−0.3 |
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−1.0 |
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μA |
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V |
DD |
= 15V, V |
IN |
= 15V |
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0.3 |
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10−5 |
0.3 |
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1.0 |
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μA |
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Note 5: IOH and IOL are tested one output at a time.
CD4021BC
3 |
www.fairchildsemi.com |
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