Fairchild Semiconductor CD4001BCMX, CD4001BCM, CD4001BCCW, CD4001BCSJX, CD4001BCSJ Datasheet
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October 1987
Revised January 1999
CD4001BC/CD4011BC
Quad 2-Input NOR Buffered B Series Gate •
Quad 2-Input NAND Buffered B Series Gate
General Description
The CD4001BC and CD4011BC quad gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also have buffered outputs which improve transfer characteristics by providing very high gain.
All inputs are protected against static discharge with diodes to VDD and VSS.
Features
■Low power TTL:
Fan out of 2 driving 74L compatibility: or 1 driving 74LS
■5V–10V–15V parametric ratings
■Symmetrical output characteristics
■Maximum input leakage 1 μA at 15V over full temperature range
Ordering Code:
Order Number |
Package Number |
Package Description |
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CD4001BCM |
M14A |
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow |
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CD4001BCSJ |
M14D |
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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CD4001BCN |
N14A |
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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CD4011BCM |
M14A |
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow |
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CD4011BCN |
N14A |
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignments for DIP, SOIC and SOP |
Pin Assignments for DIP and SOIC |
CD4001BC |
CD4011BC |
Top View
Top View
Gate Series B Buffered NAND Input-2 Quad • Gate Series B Buffered NOR Input-2 Quad CD4001BC/CD4011BC
© 1999 Fairchild Semiconductor Corporation |
DS005939.prf |
www.fairchildsemi.com |
CD4001BC/CD4011BC
Schematic Diagrams
CD4001BC
1/4 of device shown
J = A + B
Logical “1” = HIGH Logical “0” = LOW
All inputs protected by standard
CMOS protection circuit.
CD4011BC
1/4 of device shown
J = A • B
Logical “1” = HIGH Logical “0” = LOW
All inputs protected by standard
CMOS protection circuit.
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 1)
(Note 2) |
|
Voltage at any Pin |
−0.5V to VDD +0.5V |
Power Dissipation (PD) |
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Dual-In-Line |
700 mW |
Small Outline |
500 mW |
VDD Range |
−0.5 VDC to +18 VDC |
Storage Temperature (TS) |
−65°C to +150°C |
Lead Temperature (TL) |
260°C |
(Soldering, 10 seconds) |
DC Electrical Characteristics (Note 2)
Recommended Operating
Conditions
Operating Range (VDD) |
3 VDC to 15 VDC |
Operating Temperature Range |
|
CD4001BC, CD4011BC |
−40°C to +85°C |
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The Electrical Characteristics tables provide conditions for actual device operation.
Note 2: All voltages measured with respect to VSS unless otherwise specified.
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Symbol |
Parameter |
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Conditions |
−40°C |
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+25°C |
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+85°C |
Units |
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Min |
Max |
Min |
Typ |
Max |
Min |
Max |
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IDD |
Quiescent Device |
VDD = 5V, VIN = VDD or VSS |
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1 |
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0.004 |
1 |
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7.5 |
μA |
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Current |
VDD = 10V, VIN = VDD or VSS |
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2 |
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0.005 |
2 |
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15 |
μA |
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VDD = 15V, VIN = VDD or VSS |
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4 |
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0.006 |
4 |
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30 |
μA |
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VOL |
LOW Level |
VDD = 5V |
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0.05 |
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0 |
0.05 |
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0.05 |
V |
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Output Voltage |
VDD = 10V |
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|IO| < 1 μA |
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0.05 |
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0 |
0.05 |
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0.05 |
V |
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VDD = 15V |
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0.05 |
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0 |
0.05 |
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0.05 |
V |
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VOH |
HIGH Level |
VDD = 5V |
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4.95 |
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4.95 |
5 |
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4.95 |
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V |
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Output Voltage |
VDD = 10V |
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|IO| < 1 μA |
9.95 |
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9.95 |
10 |
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9.95 |
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V |
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VDD = 15V |
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14.95 |
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14.95 |
15 |
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14.95 |
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V |
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VIL |
LOW Level |
VDD = 5V, VO = 4.5V |
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1.5 |
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2 |
1.5 |
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1.5 |
V |
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Input Voltage |
VDD = 10V, VO = 9.0V |
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3.0 |
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4 |
3.0 |
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3.0 |
V |
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VDD = 15V, VO = 13.5V |
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4.0 |
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6 |
4.0 |
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4.0 |
V |
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VIH |
HIGH Level |
VDD = 5V, VO = 0.5V |
3.5 |
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3.5 |
3 |
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3.5 |
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V |
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Input Voltage |
VDD = 10V, VO = 1.0V |
7.0 |
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7.0 |
6 |
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7.0 |
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V |
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VDD = 15V, VO = 1.5V |
11.0 |
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11.0 |
9 |
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11.0 |
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V |
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IOL |
LOW Level Output |
VDD = 5V, VO = 0.4V |
0.52 |
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0.44 |
0.88 |
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0.36 |
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mA |
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Current |
VDD = 10V, VO = 0.5V |
1.3 |
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1.1 |
2.25 |
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0.9 |
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mA |
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(Note 3) |
VDD = 15V, VO = 1.5V |
3.6 |
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3.0 |
8.8 |
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2.4 |
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mA |
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IOH |
HIGH Level Output |
VDD = 5V, VO = 4.6V |
−0.52 |
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−0.44 |
−0.88 |
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−0.36 |
|
mA |
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Current |
VDD = 10V, VO = 9.5V |
−1.3 |
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−1.1 |
−2.25 |
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−0.9 |
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mA |
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(Note 3) |
VDD = 15V, VO = 13.5V |
−3.6 |
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−3.0 |
−8.8 |
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−2.4 |
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mA |
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I |
IN |
Input Current |
V |
DD |
= 15V, V |
IN |
= 0V |
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−0.30 |
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−10−5 |
−0.30 |
|
−1.0 |
μA |
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V |
DD |
= 15V, V |
IN |
= 15V |
|
0.30 |
|
10−5 |
0.30 |
|
1.0 |
μA |
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Note 3: IOL and IOH are tested one output at a time.
AC Electrical Characteristics |
(Note 4) |
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CD4001BC: TA = 25°C, Input tr; tf = 20 ns. CL = 50 pF, RL = 200k. Typical temperature coefficient is 0.3%/°C. |
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Symbol |
Parameter |
Conditions |
Typ |
Max |
Units |
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tPHL |
Propagation Delay Time, |
VDD = 5V |
120 |
250 |
ns |
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HIGH-to-LOW Level |
VDD = 10V |
50 |
100 |
ns |
|
|
VDD = 15V |
35 |
70 |
ns |
tPLH |
Propagation Delay Time, |
VDD = 5V |
110 |
250 |
ns |
|
LOW-to-HIGH Level |
VDD = 10V |
50 |
100 |
ns |
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|
VDD = 15V |
35 |
70 |
ns |
tTHL, tTLH |
Transition Time |
VDD = 5V |
90 |
200 |
ns |
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VDD = 10V |
50 |
100 |
ns |
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VDD = 15V |
40 |
80 |
ns |
CIN |
Average Input Capacitance |
Any Input |
5 |
7.5 |
pF |
CPD |
Power Dissipation Capacity |
Any Gate |
14 |
|
pF |
Note 4: AC Parameters are guaranteed by DC correlated testing.
CD4001BC/CD4011BC
3 |
www.fairchildsemi.com |
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