October 1987
Revised January 1999
CD4071BC • CD4081BC
Quad 2-Input OR Buffered B Series Gate • Quad 2-Input AND Buffered B Series Gate
General Description
The CD4071BC and CD4081BC quad gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also have buffered outputs which improve transfer characteristics by providing very high gain.
All inputs protected against static discharge with diodes to VDD and VSS.
Features
■ Low power TTL compatibility:
Fan out of 2 driving 74L or 1 driving 74LS
■5V–10V–15V parametric ratings
■Symmetrical output characteristics
■Maximum input leakage 1 μA at 15V over full temperature range
Ordering Code:
Order Number |
Package Number |
Package Description |
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CD4071BCM |
M14A |
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow |
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CD4071BCN |
N14A |
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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|
CD4081BCM |
M14A |
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow |
|
|
|
CD4081BCN |
N14A |
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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|
Devices are also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignments for DIP and SOIC
CD4071B |
CD4081B |
Top View |
Top View |
Gate Series B Buffered AND Input-2 Quad • Gate Series B Buffered OR Input-2 Quad CD4081BC • CD4071BC
© 1999 Fairchild Semiconductor Corporation |
DS005977.prf |
www.fairchildsemi.com |
CD4071BC • CD4081BC
Schematic Diagrams
CD4071B
1/4 of device shown
J = A + B
Logical “1” = HIGH Logical “0” = LOW
*All inputs protected by standard CMOS protection circuit.
CD4081B
1/4 of device shown
J = A • B
Logical “1” = HIGH Logical “0” = LOW
All inputs protected by standard CMOS protection circuit.
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 1)
(Note 2) |
|
Voltage at Any Pin |
−0.5V to VDD +0.5V |
Power Dissipation (PD) |
|
Dual-In-Line |
700 mW |
Small Outline |
500 mW |
VDD Range |
−0.5 VDC to +18 VDC |
Storage Temperature (TS) |
−65°C to +150°C |
Lead Temperature (TL) |
260°C |
(Soldering, 10 seconds) |
DC Electrical Characteristics (Note 2)
CD4071BC/CD4081BC
Recommended Operating
Conditions
Operating Range (VDD) |
3 VDC to 15 VDC |
Operating Temperature Range (TA) |
−40°C to +85°C |
CD4071BC, CD4081BC |
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation.
Note 2: All voltages measured with respect to VSS unless otherwise specified.
Symbol |
Parameter |
|
|
Conditions |
−40°C |
|
+25°C |
|
+85°C |
Units |
||||
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Min |
Max |
Min |
Typ |
Max |
Min |
Max |
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IDD |
Quiescent Device |
VDD = 5V |
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1 |
|
0.004 |
1 |
|
7.5 |
μA |
||
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Current |
VDD = 10V |
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|
2 |
|
0.005 |
2 |
|
15 |
μA |
||
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VDD = 15V |
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4 |
|
0.006 |
4 |
|
30 |
μA |
||
VOL |
LOW Level |
VDD = 5V |
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|
0.05 |
|
0 |
0.05 |
|
0.05 |
V |
||
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Output Voltage |
VDD = 10V |
|
|IO| < 1 μA |
|
0.05 |
|
0 |
0.05 |
|
0.05 |
V |
||
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VDD = 15V |
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|
0.05 |
|
0 |
0.05 |
|
0.05 |
V |
||
VOH |
HIGH Level |
VDD = 5V |
|
|
4.95 |
|
4.95 |
5 |
|
4.95 |
|
V |
||
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Output Voltage |
VDD = 10V |
|
|IO| < 1 μA |
9.95 |
|
9.95 |
10 |
|
9.95 |
|
V |
||
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|
VDD = 15V |
|
|
14.95 |
|
14.95 |
15 |
|
14.95 |
|
V |
||
VIL |
LOW Level |
VDD = 5V, VO = 0.5V |
|
1.5 |
|
2 |
1.5 |
|
1.5 |
V |
||||
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Input Voltage |
VDD = 10V, VO = 1.0V |
|
3.0 |
|
4 |
3.0 |
|
3.0 |
V |
||||
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|
VDD = 15V, VO = 1.5V |
|
4.0 |
|
6 |
4.0 |
|
4.0 |
V |
||||
VIH |
HIGH Level |
VDD = 5V, VO = 4.5V |
3.5 |
|
3.5 |
3 |
|
3.5 |
|
V |
||||
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Input Voltage |
VDD = 10V, VO = 9.0V |
7.0 |
|
7.0 |
6 |
|
7.0 |
|
V |
||||
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VDD = 15V, VO = 13.5V |
11.0 |
|
11.0 |
9 |
|
11.0 |
|
V |
||||
IOL |
LOW Level Output |
VDD = 5V, VO = 0.4V |
0.52 |
|
0.44 |
0.88 |
|
0.36 |
|
mA |
||||
|
Current |
VDD = 10V, VO = 0.5V |
1.3 |
|
1.1 |
2.25 |
|
0.9 |
|
mA |
||||
|
(Note 3) |
VDD = 15V, VO = 1.5V |
3.6 |
|
3.0 |
8.8 |
|
2.4 |
|
mA |
||||
IOH |
HIGH Level Output |
VDD = 5V, VO = 4.6V |
−0.52 |
|
−0.44 |
−0.88 |
|
−0.36 |
|
mA |
||||
|
Current |
VDD = 10V, VO = 9.5V |
−1.3 |
|
−1.1 |
−2.25 |
|
−0.9 |
|
mA |
||||
|
(Note 3) |
VDD = 15V, VO = 13.5V |
−3.6 |
|
−3.0 |
−8.8 |
|
−2.4 |
|
mA |
||||
I |
Input Current |
V |
DD |
= 15V, V |
IN |
= 0V |
|
−0.30 |
|
−10−5 |
−0.30 |
|
−1.0 |
μA |
IN |
|
|
= 15V, V |
= 15V |
|
|
|
10−5 |
|
|
|
μA |
||
|
|
V |
DD |
IN |
|
0.30 |
|
0.30 |
|
1.0 |
||||
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Note 3: IOH and IOL are tested one output at a time.
AC Electrical Characteristics (Note 4)
CD4071BC TA = 25°C, Input tr; tf = 20 ns, CL = 50 pF, RL = 200 kΩ, Typical temperature coefficient is 0.3%/°C
Symbol |
Parameter |
|
Conditions |
Typ |
Max |
Units |
|
|
|
|
|
|
|
tPHL |
Propagation Delay Time, |
VDD = 5V |
|
100 |
250 |
ns |
|
HIGH-to-LOW Level |
VDD = 10V |
|
40 |
100 |
ns |
|
|
VDD = 15V |
|
30 |
70 |
ns |
tPLH |
Propagation Delay Time, |
VDD = 5V |
|
90 |
250 |
ns |
|
LOW-to-HIGH Level |
VDD = 10V |
|
40 |
100 |
ns |
|
|
VDD = 15V |
|
30 |
70 |
ns |
tTHL, tTLH |
Transition Time |
VDD = 5V |
|
90 |
200 |
ns |
|
|
VDD = 10V |
|
50 |
100 |
ns |
|
|
VDD = 15V |
|
40 |
80 |
ns |
CIN |
Average Input Capacitance |
Any Input |
|
5 |
7.5 |
pF |
CPD |
Power Dissipation Capacity |
Any Gate |
|
18 |
|
pF |
Note 4: AC Parameters are guaranteed by DC correlated testing.
CD4081BC • CD4071BC
3 |
www.fairchildsemi.com |
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