Fairchild Semiconductor CD4066BCSJX, CD4066BCSJ, CD4066BCN, CD4066BCMX, CD4066BCM Datasheet
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November 1983
Revised August 2000
CD4066BC
Quad Bilateral Switch
General Description
The CD4066BC is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals. It is pin-for-pin compatible with CD4016BC, but has a much lower “ON” resistance, and “ON” resistance is relatively constant over the input-signal range.
Features
■ Wide supply voltage range |
3V to 15V |
■ High noise immunity 0.45 VDD (typ.) |
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■ Wide range of digital and |
± 7.5 VPEAK |
analog switching |
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■ “ON” resistance for 15V operation 80Ω
■Matched “ON” resistance ∆ RON = 5Ω (typ.) over 15V signal input
■“ON” resistance flat over peak-to-peak signal range
■High “ON”/“OFF” 65 dB (typ.)
output voltage ratio @ fis = 10 kHz, RL = 10 kΩ
■ High degree linearity |
0.1% distortion (typ.) |
High degree linearity |
@ fis = 1 kHz, Vis = 5Vp-p, |
High degree linearity |
VDD− VSS = 10V, RL = 10 kΩ |
■ Extremely low “OFF” 0.1 nA (typ.) |
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switch leakage: |
@ VDD− VSS = 10V, TA = |
25° C |
■ Extremely high control input impedance |
1012Ω (typ.) |
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■ Low crosstalk |
− 50 dB (typ.) |
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between switches @ fis = 0.9 MHz, RL = |
1 kΩ |
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■ Frequency response, switch “ON” 40 MHz (typ.)
Applications
•Analog signal switching/multiplexing
•Signal gating
•Squelch control
•Chopper
•Modulator/Demodulator
•Commutating switch
•Digital signal switching/multiplexing
•CMOS logic implementation
•Analog-to-digital/digital-to-analog conversion
•Digital control of frequency, impedance, phase, and analog-signal-gain
Ordering Code:
Order Number |
Package Number |
Package Description |
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CD4066BCM |
M14A |
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow |
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CD4066BCSJ |
M14D |
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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CD4066BCN |
N14A |
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide |
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Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram |
Schematic Diagram |
Switch Bilateral Quad CD4066BC
© 2000 Fairchild Semiconductor Corporation |
DS005665 |
www.fairchildsemi.com |
CD4066BC
Absolute Maximum Ratings
(Note 1) |
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(Note 2) |
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Supply Voltage (VDD) |
− 0.5V to + 18V |
Input Voltage (VIN) |
− 0.5V to VCC+ 0.5V |
Storage Temperature Range (TS) |
− 65° C to + 150° C |
Power Dissipation (PD) |
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Dual-In-Line |
700 mW |
Small Outline |
500 mW |
Lead Temperature (TL) |
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(Soldering, 10 seconds) |
300° C |
DC Electrical Characteristics (Note 2)
Recommended Operating
Conditions (Note 2)
Supply Voltage (V |
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3V to 15V |
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DD |
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Input Voltage (V ) |
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0V to V |
DD |
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IN |
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Operating Temperature Range (TA) |
− 40° C to + 85° C |
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Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The tables of “Recommended Operating Conditions” and “Electrical Characteristics” provide conditions for actual device operation.
Note 2: VSS = 0V unless otherwise specified.
Symbol |
Parameter |
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Conditions |
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− 40° C |
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+ 25° C |
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+ 85° C |
Units |
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Min |
Max |
Min |
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Typ |
Max |
Min |
Max |
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IDD |
Quiescent Device Current |
VDD = |
5V |
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1.0 |
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0.01 |
1.0 |
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7.5 |
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A |
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VDD = |
10V |
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2.0 |
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0.01 |
2.0 |
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15 |
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A |
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VDD = |
15V |
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4.0 |
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0.01 |
4.0 |
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30 |
µ |
A |
SIGNAL INPUTS AND OUTPUTS |
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RON |
“ON” Resistance |
RL = 10 kΩ |
to (VDD − |
VSS/2) |
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VC = |
VDD, VSS to VDD |
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VDD = |
5V |
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850 |
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270 |
1050 |
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1200 |
Ω |
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VDD = |
10V |
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330 |
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120 |
400 |
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520 |
Ω |
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VDD = |
15V |
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210 |
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80 |
240 |
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300 |
Ω |
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∆ RON |
∆ “ON” Resistance Between |
RL = 10 kΩ |
to (VDD − |
VSS/2) |
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Any 2 of 4 Switches |
VCC = |
V DD, VIS = VSS to VDD |
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VDD = |
10V |
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10 |
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Ω |
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VDD = |
15V |
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5 |
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Ω |
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IIS |
Input or Output Leakage |
VC = |
0 |
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± 50 |
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± 0.1 |
± 50 |
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± |
200 |
nA |
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Switch “OFF” |
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CONTROL INPUTS |
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VILC |
LOW Level Input |
VIS = |
V SS and VDD |
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Voltage |
VOS = |
V DD and VSS |
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IIS = ± 10µ A |
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VDD = |
5V |
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1.5 |
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2.25 |
1.5 |
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1.5 |
V |
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VDD = |
10V |
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3.0 |
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4.5 |
3.0 |
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3.0 |
V |
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VDD = |
15V |
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4.0 |
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6.75 |
4.0 |
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4.0 |
V |
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VIHC |
HIGH Level Input |
VDD = |
5V |
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3.5 |
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3.5 |
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2.75 |
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3.5 |
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V |
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Voltage |
VDD = |
10V (Note 7) |
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7.0 |
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7.0 |
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5.5 |
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7.0 |
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V |
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VDD = |
15V |
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11.0 |
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11.0 |
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8.25 |
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11.0 |
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V |
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IIN |
Input Current |
VDD− |
VSS = |
15V |
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± 0.3 |
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± |
10− 5 |
± 0.3 |
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1.0 |
µ |
A |
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VDD≥ VIS≥ V SS |
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VDD≥ VC≥ V SS |
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www.fairchildsemi.com |
2 |
AC Electrical Characteristics |
(Note 3) |
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TA = 25° C, tr = tf = 20 ns and VSS = 0V unless otherwise noted |
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Symbol |
Parameter |
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Conditions |
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Min |
Typ |
Max |
Units |
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tPHL, tPLH |
Propagation Delay Time Signal |
VC = |
VDD, CL = 50 pF, (Figure 1) |
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Input to Signal Output |
RL = |
200k |
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VDD = |
5V |
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25 |
55 |
ns |
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VDD = |
10V |
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15 |
35 |
ns |
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VDD = |
15V |
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10 |
25 |
ns |
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tPZH, tPZL |
Propagation Delay Time |
RL = |
1.0 kΩ |
, CL = |
50 pF, (Figure 2, Figure 3) |
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Control Input to Signal |
VDD = |
5V |
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125 |
ns |
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Output High Impedance to |
VDD = |
10V |
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60 |
ns |
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Logical Level |
VDD = |
15V |
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50 |
ns |
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tPHZ, tPLZ |
Propagation Delay Time |
RL = |
1.0 kΩ |
, CL = |
50 pF, (Figure 2, Figure 3) |
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Control Input to Signal |
VDD = |
5V |
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125 |
ns |
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Output Logical Level to |
VDD = |
10V |
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60 |
ns |
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High Impedance |
VDD = |
15V |
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50 |
ns |
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Sine Wave Distortion |
VC = |
VDD = |
5V, VSS = − 5V |
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0.1 |
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% |
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RL = |
10 kΩ |
, VIS = |
5Vp-p, f= 1 kHz, (Figure 4) |
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Frequency Response-Switch |
VC = |
VDD = |
5V, VSS = − 5V, |
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40 |
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MHz |
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“ON” (Frequency at − 3 dB) |
RL = |
1 kΩ |
, VIS = |
5Vp-p, |
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20 Log10 VOS/VOS (1 kHz)− dB, |
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(Figure 4) |
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Feedthrough — Switch “OFF” |
VDD = |
5.0V, VCC = VSS = − 5.0V, |
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1.25 |
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(Frequency at − 50 dB) |
RL = |
1 kΩ |
, VIS = |
5.0Vp-p, 20 Log10, |
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VOS/VIS = |
− 50 dB, (Figure 4) |
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Crosstalk Between Any Two |
VDD = |
VC(A) = 5.0V; VSS = VC(B) = 5.0V, |
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0.9 |
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MHz |
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Switches (Frequency at − 50 dB) |
RL1 kΩ |
, VIS(A) = 5.0 Vp-p, 20 Log10, |
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VOS(B)/VIS(A) = − 50 dB (Figure 5) |
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Crosstalk; Control Input to |
VDD = |
10V, RL = |
10 kΩ , RIN = |
1.0 kΩ , |
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150 |
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mVp-p |
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Signal Output |
VCC = |
10V |
Square Wave, CL = |
50 pF |
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(Figure 6) |
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Maximum Control Input |
RL = |
1.0 kΩ |
, CL = |
50 pF, (Figure 7) |
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VOS(f) = |
½ |
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VOS(1.0 kHz) |
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VDD = |
5.0V |
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6.0 |
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MHz |
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VDD = |
10V |
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8.0 |
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MHz |
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VDD = |
15V |
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8.5 |
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MHz |
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CIS |
Signal Input Capacitance |
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8.0 |
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pF |
COS |
Signal Output Capacitance |
VDD = |
10V |
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8.0 |
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pF |
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CIOS |
Feedthrough Capacitance |
VC = |
0V |
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0.5 |
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pF |
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CIN |
Control Input Capacitance |
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5.0 |
7.5 |
pF |
Note 3: AC Parameters are guaranteed by DC correlated testing.
Note 4: These devices should not be connected to circuits with the power “ON”.
Note 5: In all cases, there is approximately 5 pF of probe and jig capacitance in the output; however, this capacitance is included in CL wherever it is specified.
Note 6: |
VIS is the voltage at the in/out pin and VOS is the voltage at the out/in pin. |
VC is the voltage at the control input. |
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Note 7: |
Conditions for VIHC: a) VIS = VDD, IOS = standard B series IOH |
b) VIS = |
0V, IOL = standard B series IOL. |
CD4066BC
3 |
www.fairchildsemi.com |
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