September 1995
Revised March 1999
CGS3311 • CGS3312 • CGS3313 • CGS3314 • CGS3315 • CGS3316 • CGS3317 • CGS3318 • CGS3319
CMOS Crystal Clock Generators
General Description
The CGS3311, CGS3312, CGS3313, CGS3314, CGS3315, CGS3316, CGS3317, CGS3318 and CGS3319 devices are designed for Clock Generation and Support (CGS) applications up to 110 MHz. The CGS331x series of devices are crystal controlled CMOS oscillators requiring a minimum of external components. The 331x devices provide selectable output divide ratio (and selectable crystal drive level). The circuit is designed to operate over a wide frequency range using fundamental model or overtone crystals.
Features
■Fairchild’s CGS family of devices for high frequency clock source applications
■Crystal frequency operation range: fundamental: 10 MHz to 100 MHz typical 3rd or 5th overtone: 10 MHz to 85 MHz
■Programmable oscillator drive
■Selectable fast output edge rates
■Output symmetry circuit to adjust 50% duty cycle point between CMOS and TTL levels
■Output current drive of 48 mA for IOL/IOH
■FACTä CMOS output levels
■Output has high speed short circuit protection
■Basic oscillator type: Pierce
■Hysteresis inputs to improve noise margin
Ordering Code:
Order Number |
Package Number |
Package Description |
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CGS3311M |
M08A |
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body |
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CGS3312M |
M08A |
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body |
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CGS3313M |
M08A |
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body |
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CGS3314M |
M08A |
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body |
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CGS3315M |
M08A |
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body |
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CGS3316M |
M08A |
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body |
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CGS3317M |
M08A |
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body |
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CGS3318M |
M08A |
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body |
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CGS3319M |
M08A |
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
FACTä is a trademark of Fairchild Semiconductor Corporation.
Generators Clock |
CGS3312 • CGS3311 |
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Crystal CMOS CGS3319 • CGS3318 • CGS3317 • CGS3316 • CGS3315 • CGS3314 • CGS3313 • |
© 1999 Fairchild Semiconductor Corporation |
DS010980.prf |
www.fairchildsemi.com |
CGS3311 • CGS3312 • CGS3313 • CGS3314 • CGS3315 • CGS3316 • CGS3317 • CGS3318 • CGS3319
Connection Diagrams
(A) 3311 |
(E) 3315 |
(B)3312 |
(F) 3316 |
(C) 3313 |
(G) 3317 |
(D) 3314 |
(H) 3318 |
(I) 3319
www.fairchildsemi.com |
2 |
Truth Tables
Division Selection
DIVB |
DIVA |
OEL |
OEH |
Divider Output |
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F |
0/F |
X |
X |
Divide-by 1 |
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1 |
0/F |
0 |
1 |
Divide-by 2 |
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0 |
0/F |
0 |
1 |
Divide-by 4 |
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F |
1 |
0 |
1 |
Divide-by 8 |
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1 |
1 |
0 |
1 |
Divide-by 16 |
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0 |
1 |
0 |
1 |
Divide-by 32 |
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X |
X |
1 |
X |
Output Reset HIGH |
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at Re-enable |
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X |
X |
X |
0 |
Output Reset HIGH |
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at Re-enable |
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Note: Actual value of the floating OSC_DR and DIVB input is VCC/2
Rise and Fall Time Selection
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OSC_DR |
DIV |
TRF |
Rise/Fall Time (ns) |
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F |
N |
0/F |
2 |
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F |
N |
1 |
less than 2 |
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F |
Y |
0/F |
4 |
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F |
Y |
1 |
2 |
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0,1 |
X |
0/F |
4 |
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0,1 |
X |
1 |
2 |
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Drive Selection |
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OSC_DR |
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Drive |
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0 |
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Low |
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1 |
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Medium |
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F |
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High |
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Note: Where “F” indicates floating the input.
Pin Descriptions
Note: Pin out varies for each device. |
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OSC_IN |
Input to Oscillator Inverter. The output of the |
OEL |
Active LOW 3-STATE enable pin. This pin pulls |
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crystal would be connected here. |
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to a low value when left floating and 3-STATE |
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the output when forced HIGH. This pin has TTL |
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compatible input levels. |
OSC_OUT |
Resistive Buffered Output of the Oscillator |
TRF |
Rise and Fall time override pin. Available only |
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Inverter |
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for die form. |
OSC_DR |
3 Level input pin that selects Oscillator Drive |
OUT |
This pin is the main clock output on the device. |
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Level |
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DIVA |
Input used to select Binary Divide-by Option. |
OSCLO_1 |
The Oscillator LOW pin is the ground for the |
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This pin has CMOS compatible input levels. |
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Oscillator. |
OEH |
Active HIGH 3-STATE enable pin. This pin pulls |
OSCLO_2 |
This pin is the same signal as OSCLO_1. It has |
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to a high value when left floating and 3-STATEs |
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been provided as an alternate connection for |
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the output when forced low. This pin has TTL |
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OSCLO_1 for hybrid assemblies. |
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compatible input levels. |
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VCC |
The power pin for the chip. |
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GND |
The ground pin for all sections of the circuitry |
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except the oscillator and oscillator related |
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circuitry. |
Functional Table
Summary of Device Options
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Each drive has one output with the choices of selecting frequency divide, |
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Output Rise/ |
output enable, crystal drive and output rise and fall time. Crystal drive |
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Device |
Divide |
Enable |
Drive |
Fall Time (ns) |
options are: |
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L = LOW Drive |
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3311 |
1, 2, 4 |
OEH |
L, M, H |
2, 4 |
M = MEDIUM Drive |
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H = HIGH Drive |
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3312 |
1, 2, 4 |
OEH |
H |
2, 4 |
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3313 |
8, 16, 32 |
OEH |
H |
4 |
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3314 |
8, 16, 32 |
OEH |
L, M, H |
4 |
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3315 |
1, 2, 4 |
OEL |
H |
1, 2 |
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3316 |
4 |
OEH |
H |
4 |
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3317 |
32 |
OEH |
H |
4 |
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3318 |
1, 2, 4 |
OEH |
H |
1, 2 |
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3319 |
1, 2, 4 |
OEL |
L, M, H |
2, 4 |
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CGS3319 • CGS3318 • CGS3317 • CGS3316 • CGS3315 • CGS3314 • CGS3313 • CGS3312 • CGS3311
3 |
www.fairchildsemi.com |
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