October 1987
Revised January 1999
CD4724BC
8-Bit Addressable Latch
General Description
The CD4724BC is an 8-bit addressable latch with three address inputs (A0–A2), an active low enable input (E), active high clear input (CL), a data input (D) and eight outputs (Q0–Q7).
Data is entered into a particular bit in the latch when that is
addressed by the address inputs and the enable (E) is LOW. Data entry is inhibited when enable (E) is HIGH.
When clear (CL) and enable (E) are HIGH, all outputs are LOW. When clear (CL) is HIGH and enable (E) is LOW, the channel demultiplexing occurs. The bit that is addressed has an active output which follows the data input while all unaddressed bits are held LOW. When operating in the addressable latch mode (E = CL = LOW), changing more than one bit of the address could impose a transient wrong
address. Therefore, this should only be done while in the memory mode (E = HIGH, CL = LOW).
Features
■Wide supply voltage range: 3.0V to 15V
■High noise immunity: 0.45 VDD (typ.)
■Low power TTL compatibility:
fan out of 2 driving 74L or 1 driving 74LS
■Serial to parallel capability
■Storage register capability
■Random (addressable) data entry
■Active high demultiplexing capability
■Common active high clear
Ordering Code:
Order Number |
Package Number |
Package Description |
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CD4724BCM |
M16A |
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body |
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CD4724BCN |
N16E |
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram |
Truth Table |
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Pin Assignments for DIP and SOIC |
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Mode Selection |
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CL |
Addressed |
Unaddressed |
Mode |
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E |
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Latch |
Latch |
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L |
L |
Follows Data |
Holds Previous |
Addressable |
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Data |
Latch |
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H |
L |
Hold Previous |
Holds Previous |
Memory |
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Data |
Data |
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L |
H |
Follows Data |
Reset to “0” |
Demultiplexer |
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H |
H |
Reset to “0” |
Reset to “0” |
Clear |
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Top View
Latch Addressable Bit-8 CD4724BC
© 1999 Fairchild Semiconductor Corporation |
DS006003.prf |
www.fairchildsemi.com |
CD4724BC
Logic Diagram
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 1)
(Note 2) |
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DC Supply Voltage (VDD) |
−0.5V to +18 |
VDC |
Input Voltage (VIN) |
−0.5V to VDD +0.5 |
VDC |
Storage Temperature (TS) |
−65°C to +150°C |
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Power Dissipation (PD) |
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Dual-In-Line |
700 mW |
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Small Outline |
500 mW |
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Lead Temperature (TL) |
260°C |
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(Soldering, 10 seconds) |
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DC Electrical Characteristics (Note 2)
Recommended Operating
Conditions (Note 2)
DC Supply Voltage (VDD) |
3.0V to 15 VDC |
Input Voltage (VIN) |
0V to VDD VDC |
Operating Temperature Range (TA) |
−40°C to +85°C |
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices should be operated at these limits. The tables of “Recommended Operating Conditions” and Electrical Characteristics” provide conditions for actual device operation.
Note 2: VSS = 0V unless otherwise specified.
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Symbol |
Parameter |
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Conditions |
−40°C |
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+25°C |
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+85°C |
Units |
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Min |
Max |
Min |
Typ |
Max |
Min |
Max |
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IDD |
Quiescent Device |
VDD = 5V |
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20 |
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0.02 |
20 |
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150 |
μA |
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Current |
VDD = 10V |
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40 |
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0.02 |
40 |
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300 |
μA |
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VDD = 15V |
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80 |
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0.02 |
80 |
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600 |
μA |
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VOL |
LOW Level |
|IO| ≤ 1 μA |
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Output Voltage |
VDD = 5V |
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0.05 |
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0 |
0.05 |
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0.05 |
V |
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VDD = 10V |
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0.05 |
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0 |
0.05 |
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0.05 |
V |
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VDD = 15V |
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0.05 |
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0 |
0.05 |
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0.05 |
V |
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VOH |
HIGH Level |
|IO| ≤ 1 μA |
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Output Voltage |
VDD = 5V |
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4.95 |
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4.95 |
5.0 |
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4.95 |
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V |
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VDD = 10V |
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9.95 |
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9.95 |
10 |
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9.95 |
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V |
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VDD = 15V |
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14.95 |
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14.95 |
15 |
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14.95 |
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V |
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VIL |
LOW Level |
VDD = 5V, VO = 0.5V or 4.5V |
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1.5 |
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2.25 |
1.5 |
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1.5 |
V |
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Input Voltage |
VDD = 10V, VO = 1V or 9V |
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3.0 |
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4.5 |
3.0 |
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3.0 |
V |
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VDD = 15V, VO = 1.5V or 13.5V |
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4.0 |
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6.75 |
4.0 |
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4.0 |
V |
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VIH |
HIGH Level |
VDD = 5V, VO = 0.5V or 4.5V |
3.5 |
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3.5 |
2.75 |
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3.5 |
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V |
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Input Voltage |
VDD = 10V, VO = 1V or 9V |
7.0 |
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7.0 |
5.5 |
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7.0 |
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V |
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VDD = 15V, VO = 1.5V or 13.5V |
11.0 |
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11.0 |
8.25 |
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11.0 |
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V |
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IOL |
LOW Level Output |
VDD = 5V, VO = 0.4V |
0.52 |
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0.44 |
0.88 |
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0.36 |
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mA |
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Current |
VDD = 10V, VO = 0.5V |
1.3 |
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1.1 |
2.25 |
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0.9 |
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mA |
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(Note 3) |
VDD = 15V, VO = 1.5V |
3.6 |
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3.0 |
8.8 |
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2.4 |
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mA |
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IOH |
HIGH Level Output |
VDD = 5V, VO = 4.6V |
−0.52 |
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−0.44 |
−0.88 |
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−0.36 |
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mA |
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Current |
VDD = 10V, VO = 9.5V |
−1.3 |
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−1.1 |
−2.25 |
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−0.9 |
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mA |
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(Note 3) |
VDD = 15V, VO = 13.5V |
−3.6 |
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−3.0 |
−8.8 |
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−2.4 |
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mA |
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I |
IN |
Input Current |
V |
DD |
= 15V, V |
IN |
= 0V |
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−0.30 |
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−10−5 |
−0.30 |
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−1.0 |
μA |
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V |
DD |
= 15V, V |
IN |
= 15V |
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0.30 |
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10−5 |
0.30 |
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1.0 |
μA |
Note 3: IOL and IOH are tested one output at a time.
CD4724BC
3 |
www.fairchildsemi.com |
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