October 1987
Revised January 1999
CD4046BC
Micropower Phase-Locked Loop
General Description
The CD4046BC micropower phase-locked loop (PLL) consists of a low power, linear, voltage-controlled oscillator (VCO), a source follower, a zener diode, and two phase comparators. The two phase comparators have a common signal input and a common comparator input. The signal input can be directly coupled for a large voltage signal, or capacitively coupled to the self-biasing amplifier at the signal input for a small voltage signal.
Phase comparator I, an exclusive OR gate, provides a digital error signal (phase comp. I Out) and maintains 90° phase shifts at the VCO center frequency. Between signal input and comparator input (both at 50% duty cycle), it may lock onto the signal input frequencies that are close to harmonics of the VCO center frequency.
Phase comparator II is an edge-controlled digital memory network. It provides a digital error signal (phase comp. II Out) and lock-in signal (phase pulses) to indicate a locked condition and maintains a 0° phase shift between signal input and comparator input.
The linear voltage-controlled oscillator (VCO) produces an output signal (VCO Out) whose frequency is determined by the voltage at the VCOIN input, and the capacitor and resistors connected to pin C1A, C1B, R1 and R2.
The source follower output of the VCOIN (demodulator Out) is used with an external resistor of 10 kΩ or more.
The INHIBIT input, when high, disables the VCO and source follower to minimize standby power consumption. The zener diode is provided for power supply regulation, if necessary.
Features
■Wide supply voltage range: 3.0V to 18V
■Low dynamic power consumption: 70 μW (typ.) at fo = 10 kHz, VDD = 5V
■VCO frequency: 1.3 MHz (typ.) at VDD = 10V
■Low frequency drift: 0.06%/°C at VDD = 10V with temperature
■High VCO linearity: 1% (typ.)
Applications
•FM demodulator and modulator
•Frequency synthesis and multiplication
•Frequency discrimination
•Data synchronization and conditioning
•Voltage-to-frequency conversion
•Tone decoding
•FSK modulation
•Motor speed control
Ordering Code:
Order Number |
Package Number |
Package Description |
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CD4046BCM |
M16A |
16-Lead Small Outline integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body |
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CD4046BCN |
N16E |
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for SOIC and DIP
Top View
Loop Locked-Phase Micropower CD4046BC
© 1999 Fairchild Semiconductor Corporation |
DS005968.prf |
www.fairchildsemi.com |
CD4046BC
Block Diagram
FIGURE 1.
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 1)
(Note 2) |
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DC Supply Voltage (VDD) |
−0.5 to +18 |
VDC |
Input Voltage (VIN) |
−0.5 to VDD +0.5 |
VDC |
Storage Temperature Range (TS) |
−65°C to +150°C |
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Power Dissipation (PD) |
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Dual-In-Line |
700 mW |
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Small Outline |
500 mW |
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Lead Temperature (TL) |
260°C |
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(Soldering, 10 seconds) |
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DC Electrical Characteristics (Note 2)
Recommended Operating
Conditions (Note 2)
DC Supply Voltage (VDD) |
3 to 15 VDC |
Input Voltage (VIN) |
0 to VDD VDC |
Operating Temperature Range (TA) |
−40°C to +85°C |
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Recommended Operating Conditions” and “Electrical Characteristics” provides conditions for actual device operation.
Note 2: VSS = 0V unless otherwise specified.
Symbol |
Parameter |
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Conditions |
−40°C |
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+25°C |
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+85°C |
Units |
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Min |
Max |
Min |
Typ |
Max |
Min |
Max |
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IDD |
Quiescent Device Current |
Pin 5 = VDD, Pin 14 = VDD, |
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Pin 3, 9 = VSS |
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VDD = |
5V |
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20 |
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0.005 |
20 |
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150 |
μA |
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VDD = |
10V |
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40 |
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0.01 |
40 |
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300 |
μA |
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VDD = |
15V |
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80 |
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0.015 |
80 |
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600 |
μA |
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Pin 5 = VDD, Pin 14 = Open, |
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Pin 3, 9 = VSS |
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VDD = |
5V |
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70 |
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5 |
55 |
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205 |
μA |
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VDD = |
10V |
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530 |
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20 |
410 |
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710 |
μA |
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VDD = |
15V |
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1500 |
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50 |
1200 |
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1800 |
μA |
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VOL |
LOW Level Output Voltage |
VDD = |
5V |
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0.05 |
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0 |
0.05 |
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0.05 |
V |
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VDD = |
10V |
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0.05 |
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0 |
0.05 |
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0.05 |
V |
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VDD = |
15V |
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0.05 |
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0 |
0.05 |
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0.05 |
V |
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VOH |
HIGH Level Output Voltage |
VDD = |
5V |
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4.95 |
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4.95 |
5 |
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4.95 |
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V |
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VDD = |
10V |
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9.95 |
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9.95 |
10 |
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9.95 |
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V |
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VDD = |
15V |
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14.95 |
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14.95 |
15 |
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14.95 |
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V |
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VIL |
LOW Level Input Voltage |
VDD = |
5V, VO = 0.5V or 4.5V |
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1.5 |
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2.25 |
1.5 |
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1.5 |
V |
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Comparator and Signal In |
VDD = |
10V, VO = 1V or 9V |
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3.0 |
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4.5 |
3.0 |
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3.0 |
V |
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VDD = |
15V, VO = 1.5V or 13.5V |
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4.0 |
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6.25 |
4.0 |
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4.0 |
V |
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VIH |
HIGH Level Input Voltage |
VDD = |
5V, VO = 0.5V or 4.5V |
3.5 |
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3.5 |
2.75 |
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3.5 |
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V |
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Comparator and Signal In |
VDD = |
10V, VO = 1V or 9V |
7.0 |
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7.0 |
5.5 |
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7.0 |
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V |
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VDD = |
15V, VO = 1.5V or 13.5V |
11.0 |
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11.0 |
8.25 |
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11.0 |
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V |
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IOL |
LOW Level Output Current |
VDD = |
5V, VO = 0.4V |
0.52 |
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0.44 |
0.88 |
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0.36 |
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mA |
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(Note 4) |
VDD = |
10V, VO = 0.5V |
1.3 |
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1.1 |
2.25 |
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0.9 |
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mA |
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VDD = |
15V, VO = 1.5V |
3.6 |
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3.0 |
8.8 |
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2.4 |
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mA |
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IOH |
HIGH Level Output Current |
VDD = |
5V, VO = 4.6V |
−0.52 |
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−0.44 |
−0.88 |
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−0.36 |
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mA |
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(Note 4) |
VDD = |
10V, VO = 9.5V |
−1.3 |
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−1.1 |
−2.25 |
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−0.9 |
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mA |
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VDD = 15V, VO = 13.5V |
−3.6 |
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−3.0 |
−8.8 |
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−2.4 |
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mA |
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IIN |
Input Current |
All Inputs Except Signal Input |
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−10−5 |
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V |
DD |
= 15V, V |
= 0V |
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−0.3 |
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−0.3 |
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−1.0 |
μA |
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= |
IN |
= 15V |
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10−5 |
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μA |
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V |
DD |
15V, V |
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0.3 |
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0.3 |
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1.0 |
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IN |
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CIN |
Input Capacitance |
Any Input (Note 3) |
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7.5 |
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pF |
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PT |
Total Power Dissipation |
fo = 10 kHz, R1 = 1 MΩ, |
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R2 = ∞, ςΧΟΙΝ = ς /2 |
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VDD = |
5V |
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0.07 |
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mW |
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VDD = |
10V |
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0.6 |
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mW |
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VDD = |
15V |
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2.4 |
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mW |
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Note 3: Capacitance is guaranteed by periodic testing.
Note 4: IOH and IOL are tested one output at a time.
CD4046BC
3 |
www.fairchildsemi.com |
CD4046BC
AC Electrical Characteristics (Note 5)
TA = 25°C, CL = 50 pF
Symbol |
Parameter |
Conditions |
Min |
Typ |
Max |
Units |
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VCO SECTION |
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IDD |
Operating Current |
fo = 10 kHz, R1 = 1 MW, |
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R2 = ¥, VCOΙΝ = V /2 |
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VDD = 5V |
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20 |
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mA |
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VDD = 10V |
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90 |
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mA |
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VDD = 15V |
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200 |
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mA |
fMAX |
Maximum Operating Frequency |
C1 = 50 pF, R1 = 10 kW, |
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R2 = ¥, VCOΙΝ = V |
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VDD = 5V |
0.4 |
0.8 |
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MHz |
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VDD = 10V |
0.6 |
1.2 |
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MHz |
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VDD = 15V |
1.0 |
1.6 |
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MHz |
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Linearity |
VCOIN = 2.5V ±0.3V, |
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R1 ³ 10 kW, VDD = 5V |
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1 |
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% |
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VCOIN = 5V ±2.5V, |
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R1 ³ 400 kW, VDD = 10V |
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1 |
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% |
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VCOIN = 7.5V ±5V, |
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R1 ³ 1 MW, VDD = 15V |
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1 |
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% |
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Temperature-Frequency Stability |
%/°Cµ1/f. V |
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No Frequency Offset, fMIN = 0 |
R2 = ¥ |
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VDD = 5V |
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0.12–0.24 |
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%/°C |
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VDD = 10V |
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0.04–0.08 |
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%/°C |
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VDD = 15V |
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0.015–0.03 |
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%/°C |
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Frequency Offset, fMIN ¹ 0 |
VDD = 5V |
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0.06–0.12 |
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%/°C |
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VDD = 10V |
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0.05–0.1 |
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%/°C |
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VDD = 15V |
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0.03–0.06 |
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%/°C |
VCOIN |
Input Resistance |
VDD = 5V |
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106 |
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MW |
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VDD = 10V |
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106 |
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MW |
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VDD = 15V |
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106 |
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MW |
VCO |
Output Duty Cycle |
VDD = 5V |
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50 |
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% |
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VDD = 10V |
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50 |
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% |
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VDD = 15V |
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50 |
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% |
tTHL |
VCO Output Transition Time |
VDD = 5V |
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90 |
200 |
ns |
tTHL |
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VDD = 10V |
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50 |
100 |
ns |
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VDD = 15V |
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45 |
80 |
ns |
PHASE COMPARATORS SECTION |
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RIN |
Input Resistance |
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Signal Input |
VDD = 5V |
1 |
3 |
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MW |
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VDD = 10V |
0.2 |
0.7 |
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MW |
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VDD = 15V |
0.1 |
0.3 |
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MW |
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Comparator Input |
VDD = 5V |
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106 |
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MW |
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VDD = 10V |
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106 |
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MW |
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VDD = 15V |
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106 |
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MW |
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AC-Coupled Signal Input Voltage |
CSERIES = 1000 pF |
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Sensitivity |
f = 50 kHz |
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VDD = 5V |
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200 |
400 |
mV |
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VDD = 10V |
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400 |
800 |
mV |
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VDD = 15V |
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700 |
1400 |
mV |
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www.fairchildsemi.com |
4 |
AC Electrical Characteristics (Continued)
Symbol |
Parameter |
Conditions |
Min |
Typ |
Max |
Units |
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DEMODULATOR OUTPUT |
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VCOIN- |
Offset Voltage |
RS ³ 10 kW, VDD = 5V |
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1.50 |
2.2 |
V |
VDEM |
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RS ³ 10 kW, VDD = 10V |
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1.50 |
2.2 |
V |
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RS ³ 50 kW, VDD = 15V |
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1.50 |
2.2 |
V |
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Linearity |
RS ³ 50 kW |
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VCOIN = 2.5V ±0.3V, VDD = 5V |
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0.1 |
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% |
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VCOIN = 5V ±2.5V, VDD = 10V |
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0.6 |
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% |
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VCOIN = 7.5V ±5V, VDD = 15V |
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0.8 |
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% |
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ZENER DIODE |
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VZ |
Zener Diode Voltage |
IZ = 50 mA |
6.3 |
7.0 |
7.7 |
V |
RZ |
Zener Dynamic Resistance |
IZ = 1 mA |
|
100 |
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W |
Note 5: AC Parameters are guaranteed by DC correlated testing.
Phase Comparator State Diagrams
FIGURE 2.
CD4046BC
5 |
www.fairchildsemi.com |
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