October 1987
Revised August 2000
CD4514BC• CD4515BC
4-Bit Latched/4-to-16 Line Decoders
General Description
The CD4514BC and CD4515BC are 4-to-16 line decoders with latched inputs implemented with complementary MOS (CMOS) circuits constructed with N- and P-channel enhancement mode transistors. These circuits are primarily used in decoding applications where low power dissipation and/or high noise immunity is required.
The CD4514BC (output active high option) presents a logical “1” at the selected output, whereas the CD4515BC presents a logical “0” at the selected output. The input latches are R–S type flip-flops, which hold the last input data presented prior to the strobe transition from “1” to “0”. This input data is decoded and the corresponding output is activated. An output inhibit line is also available.
Features
■Wide supply voltage range: 3.0V to 15V
■High noise immunity: 0.45 VDD (typ.)
■Low power TTL: fan out of 2 compatibility: driving 74L
■Low quiescent power dissipation:
0.025 µ W/package @ 5.0 VDC
■ Single supply operation
■ Input impedance = 1012Ω typically
■ Plug-in replacement for MC14514, MC14515
Ordering Code:
Order Number |
Package Number |
Package Diagram |
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CD4514BCWM |
M24B |
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide |
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CD4514BCN |
N24A |
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600 Wide |
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CD4515BCWM |
M24B |
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide |
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CD4515BCN |
N24A |
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600 Wide |
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Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Top View
Decoders Line 16-to-Latched/4 Bit-4 CD4515BC CD4514BC•
© 2000 Fairchild Semiconductor Corporation |
DS005994 |
www.fairchildsemi.com |
CD4514BC• CD4515BC
Truth Table
Decode Truth Table (Strobe = 1)
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Data Inputs |
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Selected Output |
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Inhibit |
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CD4514 = |
Logic “1” |
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D |
C |
B |
A |
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CD4515 = |
Logic “0” |
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0 |
0 |
0 |
0 |
0 |
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S0 |
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0 |
0 |
0 |
0 |
1 |
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S1 |
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0 |
0 |
0 |
1 |
0 |
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S2 |
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0 |
0 |
0 |
1 |
1 |
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S3 |
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0 |
0 |
1 |
0 |
0 |
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S4 |
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0 |
0 |
1 |
0 |
1 |
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S5 |
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0 |
0 |
1 |
1 |
0 |
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S6 |
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0 |
0 |
1 |
1 |
1 |
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S7 |
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0 |
1 |
0 |
0 |
0 |
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S8 |
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0 |
1 |
0 |
0 |
1 |
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S9 |
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0 |
1 |
0 |
1 |
0 |
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S10 |
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0 |
1 |
0 |
1 |
1 |
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S11 |
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0 |
1 |
1 |
0 |
0 |
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S12 |
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0 |
1 |
1 |
0 |
1 |
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S13 |
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0 |
1 |
1 |
1 |
0 |
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S14 |
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0 |
1 |
1 |
1 |
1 |
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S15 |
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1 |
X |
X |
X |
X |
All Outputs = |
0, CD4514 |
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All Outputs = |
1, CD4515 |
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X = Don’t Care
Logic Diagram
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 1) |
Recommended Operating |
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(Note 2) |
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Conditions (Note 2) |
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DC Supply Voltage (VDD) |
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− 0.5V to + 18V |
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DC Supply Voltage (VDD) |
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3V to 15V |
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Input Voltage (V ) |
− 0.5V to V |
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+ 0.5V |
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Input Voltage (V |
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0V to V |
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IN |
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DD |
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IN |
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DD |
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Storage Temperature Range (TS) |
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− 65° C to + 150° C |
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Operating Temperature Range (TA) |
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Power Dissipation (PD) |
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CD4514BC, CD4515BC |
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− 40° C to + 85° C |
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Dual-In-Line |
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700 mW |
Note 1: “Absolute Maximum Ratings” are those values beyond which the |
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Small Outline |
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500 mW |
safety of the device cannot be guaranteed. Except for “Operating Tempera- |
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ture Range” they are not meant to imply that the devices should be oper- |
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Lead Temperature (TL) |
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ated at these limits. The tables of “Recommended Operating Conditions” |
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and “Electrical Characteristics” provide conditions for actual device opera- |
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(Soldering, 10 seconds) |
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260° C |
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tion. |
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Note 2: VSS = |
0V unless otherwise specified. |
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DC Electrical Characteristics (Note 2) |
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CD4514BC, CD4515BC |
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Symbol |
Parameter |
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Conditions |
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− 40° C |
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+ 25° C |
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+ 85° C |
Units |
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Min |
Max |
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Min |
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Typ |
Max |
Min |
Max |
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IDD |
Quiescent Device |
VDD = |
5V, VIN = VDD or V SS |
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20 |
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0.005 |
20 |
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150 |
µ A |
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Current |
VDD = |
10V, VIN = |
VDD or V SS |
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40 |
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0.010 |
40 |
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300 |
µ A |
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VDD = |
15V, VIN = |
VDD or V SS |
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80 |
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0.015 |
80 |
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600 |
µ A |
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VOL |
LOW Level |
VIL = |
0V, VIH = |
VDD, |
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Output Voltage |
|IO| < |
1 µ A |
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VDD = |
5V |
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0.05 |
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0 |
0.05 |
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0.05 |
V |
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VDD = |
10V |
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0.05 |
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0 |
0.05 |
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0.05 |
V |
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VDD = |
15V |
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0.05 |
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0 |
0.05 |
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0.05 |
V |
VOH |
HIGH Level |
VIL = |
0V, VIH = |
VDD, |
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Output Voltage |
|IO| < |
1 µ A |
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VDD = |
5V |
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4.95 |
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4.95 |
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5.0 |
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4.95 |
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V |
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VDD = |
10V |
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9.95 |
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9.95 |
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10.0 |
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9.95 |
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V |
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VDD = |
15V |
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14.95 |
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14.95 |
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15.0 |
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14.95 |
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V |
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VIL |
LOW Level |
|IO| < |
1 µ A |
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Input Voltage |
VDD = |
5V, VO = |
0.5V or 4.5V |
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1.5 |
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2.25 |
1.5 |
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1.5 |
V |
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VDD = |
10V, VO = |
1.0V or 9.0V |
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3.0 |
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4.50 |
3.0 |
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3.0 |
V |
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VDD = |
15V, VO = |
1.5V or 13.5V |
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4.0 |
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6.75 |
4.0 |
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4.0 |
V |
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VIH |
HIGH Level |
|IO| < |
1 µ A |
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Input Voltage |
VDD = |
5V, VO = |
0.5V or 4.5V |
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3.5 |
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3.5 |
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2.75 |
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3.5 |
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V |
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VDD = |
10V, VO = |
1.0V or 9.0V |
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7.0 |
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7.0 |
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5.50 |
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7.0 |
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V |
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VDD = |
15V, VO = |
1.5V or 13.5V |
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11.0 |
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11.0 |
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8.25 |
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11.0 |
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V |
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IOL |
LOW Level Output |
VDD = |
5V, VO = |
0.4V |
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0.52 |
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0.44 |
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0.88 |
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0.36 |
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mA |
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Current (Note 3) |
VDD = |
10V, VO = |
0.5V |
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1.3 |
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1.1 |
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2.25 |
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0.90 |
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mA |
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VDD = |
15V, VO = |
1.5V |
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3.6 |
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3.0 |
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8.8 |
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2.4 |
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mA |
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IOH |
HIGH Level Output |
VDD = |
5V, VO = |
4.6V |
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− 0.52 |
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− 0.44 |
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− |
0.88 |
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− 0.36 |
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mA |
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Current (Note 3) |
VDD = |
10V, VO = |
9.5V |
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− 1.3 |
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− 1.1 |
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− |
2.25 |
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− 0.90 |
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mA |
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VDD = |
15V, VO = |
13.5V |
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− 3.6 |
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− 3.0 |
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− 8.8 |
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− 2.4 |
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mA |
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IIN |
Input Current |
VDD = |
15V, VIN = |
0V |
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− 0.3 |
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− |
10− 5 |
− 0.3 |
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− 1.0 |
µ A |
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VDD = |
15V, VIN = |
15V |
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0.3 |
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10− 5 |
0.3 |
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1.0 |
µ A |
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Note 3: IOH and IOL are tested one output at a time.
CD4515BC CD4514BC•
3 |
www.fairchildsemi.com |
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