September 1195
Revised March 1999
CGS3321 • CGS3322
CMOS Crystal Clock Generators
General Description
The CGS3321 and CGS3322 devices are designed for Clock Generation and Support (CGS) applications up to 110 MHz. The CGS332x series of devices are crystal controlled CMOS oscillators requiring a minimum of external components. The 332x devices provide selectable output divide ratio. The circuit is designed to operate over a wide frequency range using fundamental mode or overtone crystals.
Features
■Fairchild’s CGS family of devices for high frequency clock source applications
■Crystal frequency operation range: fundamental: 10 MHz to 100 MHz typical 3rd or 5th overtone: 10 MHz to 95 MHz
■1000V ESD protection on OCS_IN and OSC_OUT pins. 2000V ESD protection on all other pins
■Output current drive of 48 mA for IOL/IOH
■FACTä CMOS output levels
■Output has high speed short circuit protection
■Intended for Pierce oscillator applications
■Hysteresis inputs to improve noise margin
■CGS3321 has duty cycle adjust
■CGS3322 has 1, 2, 4 divide ratio
Ordering Code:
Order Number |
Package Number |
Package Description |
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CGS3321M |
M08A |
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body |
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CGS3322M |
M08A |
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams |
Truth Table |
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CGS3321 |
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Division Selection |
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DIVB |
OEH |
Divider Output |
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F |
X |
Divide-by 1 |
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1 |
1 |
Divide-by 2 |
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0 |
1 |
Divide-by 4 |
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Note: Actual value of the floating DIVB input is VCC/2
CGS3322
FACTä is a trademark of Fairchild Semiconductor Corporation.
Generators Clock Crystal CMOS CGS3322 • CGS3321
© 1999 Fairchild Semiconductor Corporation |
DS011503.prf |
www.fairchildsemi.com |
CGS3321 • CGS3322
Pin Descriptions
Note: Pin out varies for each device. |
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OSC_IN |
Input to Oscillator Inverter. The output of the |
OEH |
Active HIGH 3-STATE enable pin. This pin pulls |
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crystal would be connected here. |
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to a HIGH value when left floating and 3- |
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STATEs the output when forced LOW. This pin |
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has TTL compatible input levels. |
OSC_OUT |
Resistive Buffered Output of the Oscillator |
OUT |
This pin is the main clock output on the device. |
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Inverter |
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DIVB |
(CGS3322 only) |
OSCLO_1 |
The Oscillator LOW pin is the ground for the |
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3-Level input used to select Binary Divide-by |
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Oscillator. |
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value of output frequency. |
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DC_ADJ |
(CGS3321 only) |
VCC |
The power pin for the chip. |
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Active high input that controls output duty |
GND |
The ground pin for all sections of the circuitry |
cycle. Logic high level will delay the HL transi- |
except the oscillator and oscillator related |
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tion edge approximately 0.3 ns. |
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circuitry. |
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Note: Pin out varies for each device.
Block Diagrams
Note: Pin numbers vary for each device
www.fairchildsemi.com |
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