Fairchild Semiconductor CD4016BCN, CD4016BCMX, CD4016BCM Datasheet

November 1983

Revised January 1999

CD4016BC

Quad Bilateral Switch

General Description

The CD4016BC is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals. It is pin-for-pin compatible with CD4066BC.

Features

■Wide supply voltage range: 3V to 15V

■Wide range of digital and analog switching: ±7.5 VPEAK

■“ON” resistance for 15V operation: 400Ω (typ.)

■Matched “ON” resistance over 15V signal input:

RON = 10Ω (typ.)

■High degree of linearity: 0.4% distortion (typ.)

@fIS = 1 kHz, VIS = 5 Vp-p, VDD−VSS = 10V, RL = 10 kΩ

■Extremely low “OFF” switch leakage: 0.1 nA (typ.)

@VDD − VSS = 10V

TA = 25°C

■Extremely high control input impedance: 1012Ω (typ.)

■Low crosstalk between switches:

−50 dB (typ.)

@fIS = 0.9 MHz, RL = 1 kΩ

■Frequency response, switch “ON”: 40 MHz (typ.)

Applications

•Analog signal switching/multiplexing Signal gating

Squelch control Chopper Modulator/Demodulator Commutating switch

•Digital signal switching/multiplexing

•CMOS logic implementation

•Analog-to-digital/digital-to-analog conversion

•Digital control of frequency, impedance, phase, and ana- log-signal gain

Ordering Code:

Order Number	Package Number	Package Description
CD4016BCM	M14A	14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
CD4016BCN	N14A	14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Devices also available in Tape and Reel. Specify by appending the letter suffix “X” to the ordering code.

Connection Diagram	Schematic Diagram
Pin Assignments for DIP and SOIC

Switch Bilateral Quad CD4016BC

© 1999 Fairchild Semiconductor Corporation

DS005661.prf

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CD4016BC

Absolute Maximum Ratings(Note 1)

(Note 2)
VDD Supply Voltage	−0.5V to +18V
VIN Input Voltage	−0.5V to VDD + 0.5V
TS Storage Temperature Range	−65°C to + 150°C
Power Dissipation (PD)
Dual-In-Line	700 mW
Small Outline	500 mW
Lead Temperature
(Soldering, 10 seconds)	260°C

DC Electrical Characteristics (Note 2)

Recommended Operating

Conditions (Note 2)

VDD Supply Voltage	3V to 15V
VIN Input Voltage	0V to VDD
TA Operating Temperature Range	−40°C to +85°C

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The tables of “Recommended Operating Conditions” and “Electrical Characteristics” provide conditions for actual device operation.

Note 2: VSS = 0V unless otherwise specified.

Symbol	Parameter	Conditions	-40°C			25°C		+85°C		Units
			Min	Max	Min	Typ	Max	Min	Max
IDD	Quiescent Device	VDD = 5V, VIN = VDD or VSS		1.0		0.01	1.0		7.5	mA
	Current	VDD = 10V, VIN = VDD or VSS		2.0		0.01	2.0		15	mA
		VDD = 15V, VIN = VDD or VSS		4.0		0.01	4.0		30	mA
Signal Inputs and Outputs
RON	“ON” Resistance	RL = 10kW to (VDD - VSS)/2
		VC = VDD, VIS = VSS or VDD
		VDD = 10V		610		275	660		840	W
		VDD = 15V		370		200	400		520	W
		RL = 10kW to (VDD - VSS)/2
		VC = VDD
		VDD = 10V, VIS = 4.75 to 5.25V		1900		850	2000		2380	W
		VDD = 15V, VIS = 7.25 to 7.75V		790		400	850		1080	W
DRON	D“ON” Resistance	R L = 10kW to (VDD - VSS)/2
	Between any 2 of	VC = VDD, VIS = VSS to VDD
	4 Switches	VDD = 10V				15				W
	(In Same Package)	VDD = 15V				10				W
IIS	Input or Output	VC = 0, VDD = 15V		±50		±0.1	±50		±200	nA
	Leakage	VIS = 0V or 15V,
	Switch “OFF”	V OS = 15V or 0V
Control Inputs
VILC	LOW Level Input	VIS = VSS and VDD
	Voltage	VOS = VDD and VSS
		IIS = ±10 mA
		VDD = 5V		0.9			0.7		0.4	V
		VDD = 10V		0.9			0.7		0.4	V
		VDD = 15V		0.9			0.7		0.4	V
VIHC	HIGH Level Input	VDD = 5V	3.5		3.5			3.5		V
	Voltage	VDD = 10V	7.0		7.0			7.0		V
		VDD = 15V	11.0		11.0			11.0		V
		(Note 3) and Figure 8				±10−5
IIN	Input Current	VCC - VSS = 15V		±0.3			±0.3		±1.0	mA
		VDD ³ VIS ³ VSS
		VDD ³ VC ³ VSS

Note 3: If the switch input is held at VDD, VIHC is the control input level that will cause the switch output to meet the standard “B” series V OH and IOH output levels. If the analog switch input is connected to VSS, VIHC is the control input level — which allows the switch to sink standard “B” series |I OH|, high level current, and still maintain a VOL ≤ “B” series. These currents are shown in Figure 8.

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2

AC Electrical Characteristics (Note 4)

TA = 25°C, tr = tf = 20 ns and VSS = 0V unless otherwise specified

Symbol	Parameter	Conditions	Min	Typ	Max	Units
tPHL, tPLH	Propagation Delay Time	VC = VDD, CL = 50 pF, (Figure 1)
	Signal Input to Signal Output	RL = 200k
		VDD = 5V		58	100	ns
		VDD= 10V		27	50	ns
		VDD = 15V		20	40	ns
tPZH, tPZL	Propagation Delay Time	RL = 1.0 kΩ, CL = 50 pF, (Figure 2, Figure 3)
	Control Input to Signal	VDD = 5V		20	50	ns
	Output HIGH Impedance to	VDD = 10V		18	40	ns
	Logical Level	VDD = 15V		17	35	ns
tPHZ, tPLZ	Propagation Delay Time	RL = 1.0 kΩ, CL = 50 pF, (Figure 2, Figure 3)
	Control Input to Signal	VDD = 5V		15	40	ns
	Output Logical Level to	VDD = 10V		11	25	ns
	HIGH Impedance	VDD = 15V		10	22	ns
	Sine Wave Distortion	VC = VDD = 5V, VSS = −5		0.4		%
		RL = 10 kΩ, VIS = 5 VP-P, f = 1 kHz,
		(Figure 4)
	Frequency Response — Switch	V C = VDD = 5V, VSS = −5V,		40		MHz
	“ON” (Frequency at −3 dB)	RL = 1 kΩ, VIS = 5 VP-P,
		20 Log10 VOS/VOS (1 kHz) −dB,
		(Figure 4)
	Feedthrough — Switch “OFF”	V DD = 5V, VC = VSS = −5V,		1.25		MHz
	(Frequency at −50 dB)	RL = 1 kΩ, VIS = 5 VP-P,
		20 Log10 (VOS/VIS) = −50 dB,
		(Figure 4)
	Crosstalk Between Any Two	VDD = VC(A) = 5V; VSS = VC(B) = −5V,		0.9		MHz
	Switches (Frequency at −50 dB)	RL = 1 kΩVIS(A) = 5 VP-P,
		20 Log10 (VOS(B)/VOS(A) ) = −50 dB,
		(Figure 5)
	Crosstalk; Control Input to	VDD = 10V, RL = 10 kΩ		150		mVP-P
	Signal Output	RIN = 1 kΩ, VCC = 10V Square Wave,
		CL = 50 pF (Figure 6)
	Maximum Control Input	RL = 1 kΩ, CL = 50 pF, (Figure 7)
		VOS(f) = ½ V OS(1 kHz)
		VDD = 5V		6.5		MHz
		VDD = 10V		8.0		MHz
		VDD = 15V		9.0		MHz
CIS	Signal Input Capacitance			4		pF
COS	Signal Output Capacitance	VDD = 10V		4		pF
CIOS	Feedthrough Capacitance	VC = 0V		0.2		pF
CIN	Control Input Capacitance			5	7.5	pF

Note 4: AC Parameters are guaranteed by DC correlated testing.

Note 5: These devices should not be connected to circuits with the power “ON”.

Note 6: In all cases, there is approximately 5 pF of probe and jig capacitance on the output; however, this capacitance is included in CL wherever it is specified.

Note 7: VIS is the voltage at the in/out pin and VOS is the voltage at the out/in pin. VC is the voltage at the control input.

CD4016BC

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