Fairchild Semiconductor 74ACQ646SPC, 74ACQ646SCX, 74ACQ646SC, 74ACQ646CW Datasheet

January 1990

Revised September 2000

74ACQ646 • 74ACTQ646

Quiet Series Octal Transceiver/Register with 3-STATE Outputs

General Description

The ACQ/ACTQ646 consist of registered bus transceiver circuits, with outputs, D-type flip-flops, and control circuitry providing multiplexed transmission of data directly from the input bus or from the internal storage registers. Data on the A or B bus will be loaded into the respective registers on the LOW-to-HIGH transition of the appropriate clock pin (CPAB or CPBA). The four fundamental handling functions available are illustrated in Figure 1, Figure 2, Figure 3 and Figure 4.

The ACQ/ACTQ utilizes Fairchild Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector in addition to a split ground bus for superior performance.

Features

■Guaranteed simultaneous switching noise level and dynamic threshold performance

■Guaranteed pin-to-pin skew AC performance

■Independent registers for A and B busses

■Multiplexed real-time and stored data transfers

■300 mil slim dual-in-line package

■Outputs source/sink 24 mA

■Faster prop delays than the standard AC/ACT646

Ordering Code:

Order Number	Package Number	Package Description
74ACQ646SC	M24B	24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACQ464ASPC	N24C	24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74ACTQ646SC	M24B	24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACTQ464ASPC	N24C	24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram	Pin Descriptions
				Pin Names	Descriptions
			A0–A7		Data Register A Inputs
					Data Register A Outputs
			B0–B7		Data Register B Inputs
					Data Register B Outputs
			CPAB, CPBA		Clock Pulse Inputs
			SAB, SBA		Transmit/Receive Inputs
					Output Enable Input
			G
			DIR		Direction Control Input

FACT , Quiet Series , FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation

Outputs STATE-3 with Transceiver/Register Octal Series Quiet 74ACTQ646 • 74ACQ646

© 2000 Fairchild Semiconductor Corporation

DS010635

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74ACQ646 • 74ACTQ646

Logic Symbols

IEEE/IEC

Function Table

				Inputs				Data I/O (Note 1)		Function
			DIR	CPAB	CPBA	SAB	SBA	A0–A7	B0–B7
	G
	H		X	H or L	H or L	X	X			Isolation
	H		X		X	X	X	Input	Input	Clock An Data into A Register
	H		X	X		X	X			Clock Bn Data into B Register
	L		H	X	X	L	X			An to Bn— Real Time (Transparent Mode)
	L		H		X	L	X	Input	Output	Clock An Data into A Register
	L		H	H or L	X	H	X			A Register to Bn (Stored Mode)
	L		H		X	H	X			Clock An Data into A Register and Output to Bn
	L		L	X	X	X	L			Bn to An— Real Time (Transparent Mode)
	L		L	X		X	L	Output	Input	Clock Bn Data into B Register
	L		L	X	H or L	X	H			B Register to An (Stored Mode)
	L		L	X		X	H			Clock Bn Data into B Register and Output to An

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

= LOW-to-HIGH Transition

Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled; i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs.

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2

Real Time Transfer	Real Time Transfer
A-Bus to B-Bus	B-Bus to A-Bus

FIGURE 1.	FIGURE 2.
Storage from	Transfer from
Bus to Register	Register to Bus

FIGURE 3.

FIGURE 4.

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

74ACTQ646 • 74ACQ646

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