November 1988
Revised November 1999
74AC74 • 74ACT74
Dual D-Type Positive Edge-Triggered Flip-Flop
General Description
The AC/ACT74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q
HIGH
Features
■ICC reduced by 50%
■Output source/sink 24 mA
■ACT74 has TTL-compatible inputs
Ordering Code:
Order Number |
Package Number |
Package Description |
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74AC74SC |
M14A |
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body |
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74AC74SJ |
M14D |
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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74AC74MTC |
MTC14 |
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide |
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74AC74PC |
N14A |
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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74ACT74SC |
M14A |
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body |
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74ACT74SJ |
M14D |
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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74ACT74MTC |
MTC14 |
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide |
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74ACT74PC |
N14A |
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram |
Pin Descriptions |
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Pin Names |
Description |
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D1, D2 |
Data Inputs |
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CP1, CP2 |
Clock Pulse Inputs |
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D2 |
Direct Clear Inputs |
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C |
D1, |
C |
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D2 |
Direct Set Inputs |
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S |
D1, |
S |
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Q1, |
Q |
1, Q2, |
Q |
2 |
Outputs |
FACT is a trademark of Fairchild Semiconductor Corporation.
Flop-Flip Triggered-Edge Positive Type-D Dual 74ACT74 • 74AC74
© 1999 Fairchild Semiconductor Corporation |
DS009920 |
www.fairchildsemi.com |
74AC74 • 74ACT74
Logic Symbols
IEEE/IEC
Truth Table
(Each Half)
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Inputs |
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Outputs |
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SD |
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CD |
CP |
D |
Q |
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Q |
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L |
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H |
X |
X |
H |
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L |
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H |
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L |
X |
X |
L |
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H |
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L |
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L |
X |
X |
H |
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H |
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H |
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H |
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H |
H |
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L |
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H |
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H |
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L |
L |
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H |
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H |
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H |
L |
X |
Q0 |
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Q |
0 |
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H = HIGH Voltage Level |
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L = LOW Voltage Level |
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X = Immaterial |
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= LOW-to-HIGH Clock Transition |
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Q0 (Q0) = Previous Q (Q) before LOW-to-HIGH Transition of Clock
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) |
− 0.5V to + 7.0V |
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DC Input Diode Current (IIK) |
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VI = |
− 0.5V |
− 20 mA |
VI = |
VCC + 0.5V |
+ 20 mA |
DC Input Voltage (VI) |
− 0.5V to VCC + 0.5V |
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DC Output Diode Current (IOK) |
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VO = |
− 0.5V |
− 20 mA |
VO = |
VCC + 0.5V |
+ 20 mA |
DC Output Voltage (VO) |
− 0.5V to VCC + 0.5V |
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DC Output Source |
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or Sink Current (IO) |
± 50 mA |
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DC VCC or Ground Current |
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per Output Pin (ICC or IGND) |
± 50 mA |
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Storage Temperature (TSTG) |
− 65° C to + 150° C |
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Junction Temperature (TJ) |
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PDIP |
140° C |
Recommended Operating
Conditions
Supply Voltage (VCC) |
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AC |
2.0V to 6.0V |
ACT |
4.5V to 5.5V |
Input Voltage (VI) |
0V to VCC |
Output Voltage (VO) |
0V to VCC |
Operating Temperature (TA) |
− 40° C to + 85° C |
Minimum Input Edge Rate (∆ V/∆ t) |
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AC Devices |
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VIN from 30% to 70% of VCC |
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VCC @ 3.3V, 4.5V, 5.5V |
125 mV/ns |
Minimum Input Edge Rate (∆ V/∆ t) |
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ACT Devices |
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VIN from 0.8V to 2.0V |
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VCC @ 4.5V, 5.5V |
125 mV/ns |
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics for AC
Symbol |
Parameter |
VCC |
TA = + 25° C |
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TA = − 40° C to + 85° C |
Units |
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Conditions |
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(V) |
Typ |
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Guaranteed Limits |
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VIH |
Minimum HIGH |
3.0 |
1.5 |
2.1 |
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2.1 |
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VOUT = |
0.1V |
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Level Input |
4.5 |
2.25 |
3.15 |
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3.15 |
V |
or VCC − |
0.1V |
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Voltage |
5.5 |
2.75 |
3.85 |
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3.85 |
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VIL |
Maximum LOW |
3.0 |
1.5 |
0.9 |
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0.9 |
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VOUT = |
0.1V |
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Level Input |
4.5 |
2.25 |
1.35 |
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1.35 |
V |
or VCC − |
0.1V |
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Voltage |
5.5 |
2.75 |
1.65 |
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1.65 |
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VOH |
Minimum HIGH |
3.0 |
2.99 |
2.9 |
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2.9 |
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Level Output |
4.5 |
4.49 |
4.4 |
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4.4 |
V |
IOUT = |
− |
50 µ A |
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Voltage |
5.5 |
5.49 |
5.4 |
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5.4 |
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VIN = |
VIL or VIH |
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3.0 |
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2.56 |
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2.46 |
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IOH = |
− |
12 mA |
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4.5 |
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3.86 |
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3.76 |
V |
IOH = |
− |
24 m |
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5.5 |
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4.86 |
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4.76 |
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IOH = |
− 24 m (Note 2) |
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VOL |
Maximum LOW |
3.0 |
0.002 |
0.1 |
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0.1 |
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Level Output |
4.5 |
0.001 |
0.1 |
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0.1 |
V |
IOUT = |
50 µ A |
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Voltage |
5.5 |
0.001 |
0.1 |
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0.1 |
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VIN = |
VIL or VIH |
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3.0 |
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0.36 |
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0.44 |
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IOL = |
12 mA |
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4.5 |
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0.36 |
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0.44 |
V |
IOL = |
24 mA |
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5.5 |
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0.36 |
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0.44 |
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IOL = |
24 mA (Note 2) |
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IIN (Note 4) |
Maximum InputLeakage Current |
5.5 |
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± 0.1 |
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± 1.0 |
µ A |
VI = |
VCC, GND |
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IOLD |
Minimum Dynamic |
5.5 |
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75 |
mA |
VOLD = |
1.65V Max |
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IOHD |
Output Current (Note 3) |
5.5 |
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− 75 |
mA |
VOHD = |
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3.85V Min |
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ICC |
Maximum Quiescent |
5.5 |
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2.0 |
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20.0 |
µ A |
VIN = |
VCC |
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(Note 4) |
Supply Current |
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or GND |
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Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
74ACT74 • 74AC74
3 |
www.fairchildsemi.com |