MOTOROLA MC74VHC541M, MC74VHC541DTR2, MC74VHC541DW, MC74VHC541ML2, MC74VHC541MEL Datasheet

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MOTOROLA MC74VHC541M, MC74VHC541DTR2, MC74VHC541DW, MC74VHC541ML2, MC74VHC541MEL Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Octal Bus Buffer

The MC74VHC541 is an advanced high speed CMOS octal bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.

The MC74VHC541 is a noninverting type. When either OE1 or OE2 are high, the terminal outputs are in the high impedance state.

The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems.

High Speed: tPD = 3.7ns (Typ) at VCC = 5V

Low Power Dissipation: ICC = 4μA (Max) at TA = 25°C

High Noise Immunity: VNIH = VNIL = 28% VCC

Power Down Protection Provided on Inputs

Balanced Propagation Delays

Designed for 2V to 5.5V Operating Range

Low Noise: VOLP = 1.2V (Max)

Pin and Function Compatible with Other Standard Logic Families

Latchup Performance Exceeds 300mA

ESD Performance: HBM > 2000V; Machine Model > 200V

Chip Complexity: 134 FETs or 33.5 Equivalent Gates

LOGIC DIAGRAM

 

A1

2

18

Y1

 

 

 

 

 

 

A2

3

17

Y2

 

 

 

 

 

 

A3

4

16

Y3

 

 

A4

5

15

Y4

 

DATA

 

 

NONINVERTING

 

 

 

 

INPUTS

 

6

14

 

OUTPUTS

 

A5

Y5

 

 

A6

7

13

Y6

 

 

 

 

 

 

A7

8

12

Y7

 

 

 

 

 

 

A8

9

11

Y8

 

 

OE1

 

1

 

 

OUTPUT

 

 

 

 

 

 

 

 

 

ENABLES

OE2

 

19

 

 

 

 

 

 

 

 

 

 

 

FUNCTION TABLE

 

 

 

Inputs

 

Output Y

 

 

 

 

 

 

 

 

 

 

 

 

 

A

 

OE1

 

 

OE2

 

 

 

L

 

L

L

L

 

L

 

L

H

H

 

H

 

X

X

Z

 

X

 

H

X

Z

 

 

 

 

 

 

 

 

MC74VHC541

DW SUFFIX

20±LEAD SOIC WIDE PACKAGE

CASE 751D±04

DT SUFFIX

20±LEAD TSSOP PACKAGE

CASE 948E±02

M SUFFIX

20±LEAD SOIC EIAJ PACKAGE

CASE 967±01

ORDERING INFORMATION

MC74VHCXXXDW

SOIC WIDE

MC74VHCXXXDT

TSSOP

MC74VHCXXXM

SOIC EIAJ

PIN ASSIGNMENT

 

 

 

 

 

 

 

 

 

OE1

 

1

20

 

VCC

 

 

 

 

A1

 

2

19

 

OE2

 

A2

 

3

18

Y1

 

 

 

A3

 

4

17

Y2

 

 

 

A4

 

5

16

Y3

 

 

 

A5

 

6

15

 

Y4

 

 

 

 

A6

 

7

14

 

Y5

 

 

 

 

A7

 

8

13

 

Y6

 

 

 

 

A8

 

9

12

 

Y7

 

 

 

GND

 

10

11

 

Y8

 

 

 

 

 

 

 

 

 

 

4/98

Motorola, Inc. 1998

1

REV 2

MC74VHC541

MAXIMUM RATINGS*

Symbol

Parameter

 

Value

Unit

 

 

 

 

 

VCC

DC Supply Voltage

 

± 0.5 to + 7.0

V

Vin

DC Input Voltage

 

± 0.5 to + 7.0

V

Vout

DC Output Voltage

 

± 0.5 to VCC + 0.5

V

IIK

Input Diode Current

 

± 20

mA

IOK

Output Diode Current

 

± 20

mA

Iout

DC Output Current, per Pin

 

± 25

mA

ICC

DC Supply Current, VCC and GND Pins

± 50

mA

PD

Power Dissipation in Still Air,

SOIC Packages²

500

mW

 

 

TSSOP Package²

450

 

 

 

 

 

 

Tstg

Storage Temperature

 

± 65 to + 150

_C

*Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute±maximum±rated conditions is not implied.

²Derating Ð SOIC Packages: ± 7 mW/ _C from 65_ to 125_C TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

 

Min

Max

Unit

 

 

 

 

 

 

VCC

DC Supply Voltage

 

2.0

5.5

V

Vin

DC Input Voltage

 

0

5.5

V

Vout

DC Output Voltage

 

0

VCC

V

TA

Operating Temperature, All Package Types

± 40

+ 85

_C

tr, tf

Input Rise and Fall Time

VCC = 3.3V ±0.3V

0

100

ns/V

 

 

VCC =5.0V ±0.5V

0

20

 

DC ELECTRICAL CHARACTERISTICS

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

 

 

 

VCC

 

TA = 25°C

 

TA = ± 40 to 85°C

 

Symbol

Parameter

Test Conditions

V

Min

Typ

Max

Min

Max

Unit

 

 

 

 

 

 

 

 

 

 

VIH

Minimum High±Level

 

2.0

1.50

 

 

1.50

 

V

 

Input Voltage

 

3.0 to

VCC x 0.7

 

 

VCC x 0.7

 

 

 

 

 

5.5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VIL

Maximum Low±Level

 

2.0

 

 

0.50

 

0.50

V

 

Input Voltage

 

3.0 to

 

 

VCC x 0.3

 

VCC x 0.3

 

 

 

 

5.5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VOH

Minimum High±Level

Vin = VIH or VIL

2.0

1.9

2.0

 

1.9

 

V

 

Output Voltage

IOH = ± 50μA

3.0

2.9

3.0

 

2.9

 

 

 

 

 

4.5

4.4

4.5

 

4.4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Vin = VIH or VIL

 

 

 

 

 

 

 

 

 

IOH = ± 4mA

3.0

2.58

 

 

2.48

 

 

 

 

IOH = ± 8mA

4.5

3.94

 

 

3.80

 

 

VOL

Maximum Low±Level

Vin = VIH or VIL

2.0

 

0.0

0.1

 

0.1

V

 

Output Voltage

IOL = 50μA

3.0

 

0.0

0.1

 

0.1

 

 

 

 

4.5

 

0.0

0.1

 

0.1

 

 

 

 

 

 

 

 

 

 

 

 

 

Vin = VIH or VIL

 

 

 

 

 

 

 

 

 

IOL = 4mA

3.0

 

 

0.36

 

0.44

 

 

 

IOL = 8mA

4.5

 

 

0.36

 

0.44

 

MOTOROLA

2

VHC Data ± Advanced CMOS Logic

 

 

DL203 Ð Rev 2

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