MOTOROLA MC74VHC573ML2, MC74VHC573DWR2, MC74VHC573M, MC74VHC573MEL, MC74VHC573ML1 Datasheet

MC74VHC573

Octal D-Type Latch with 3-State Output

The MC74VHC573 is an advanced high speed CMOS octal latch with 3±state output fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.

This 8±bit D±type latch is controlled by a latch enable input and an output enable input. When the output enable input is high, the eight outputs are in a high impedance state.

The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems.

•High Speed: tPD = 4.5ns (Typ) at VCC = 5V

•Low Power Dissipation: ICC = 4μA (Max) at TA = 25°C

•High Noise Immunity: VNIH = VNIL = 28% VCC

•Power Down Protection Provided on Inputs

•Balanced Propagation Delays

•Designed for 2V to 5.5V Operating Range

•Low Noise: VOLP = 1.2V (Max)

•Pin and Function Compatible with Other Standard Logic Families

•Latchup Performance Exceeds 300mA

•ESD Performance: HBM > 2000V; Machine Model > 200V

•Chip Complexity: 218 FETs or 54.5 Equivalent Gates

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			MARKING
			DIAGRAMS
			20
		SOIC±20 WIDE	VHC573
20		DW SUFFIX
			AWLYYWW
		CASE 751D
	1
			1
			20
		TSSOP±20	VHC
20		DT SUFFIX	573
	1	CASE 948E	ALYW

1

20

SOIC EIAJ

M SUFFIX

VHC573

20 AWLYYWW

CASE 967

1	1

A = Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

PIN ASSIGNMENT

				LOGIC DIAGRAM												1	20	VCC
		D0		2					19	Q0			OE
													D0			2	19	Q0
				3					18
		D1								Q1			D1			3	18	Q1
				4					17
		D2								Q2			D2			4	17	Q2
				5					16		NONINVERTING
DATA		D3								Q3			D3			5	16	Q3
INPUTS		D4		6					15	Q4	OUTPUTS
													D4			6	15	Q4
				7					14
		D5								Q5
													D5			7	14	Q5
				8					13
		D6								Q6
				9					12				D6			8	13	Q6
		D7								Q7
				11									D7			9	12	Q7
		LE
												GND				10	11	LE
				1
		OE
FUNCTION TABLE												ORDERING INFORMATION

			INPUTS		OUTPUT
			LE	D	Q
	OE
	L		H	H	H
	L		H	L	L
	L		L	X	No Change
	H		X	X	Z

Device	Package	Shipping
MC74VHC573DW	SOIC±WIDE	38 / Rail
MC74VHC573DWR2	SOIC±WIDE	1000 / Reel
MC74VHC573DT	TSSOP±20	75 / Rail
MC74VHC573DTR2	TSSOP±20	2500 / Reel
MC74VHC573M	SOIC EIAJ	40 / Rail
MC74VHC573MEL	SOIC EIAJ	2000 / Reel

Semiconductor Components Industries, LLC, 2000	1	Publication Order Number:
April, 2000 ± Rev. 3		MC74VHC573/D

MC74VHC573

MAXIMUM RATINGS*

Symbol	Parameter		Value	Unit
VCC	DC Supply Voltage		± 0.5 to + 7.0	V
Vin	DC Input Voltage		± 0.5 to + 7.0	V
Vout	DC Output Voltage		± 0.5 to VCC + 0.5	V
IIK	Input Diode Current		± 20	mA
IOK	Output Diode Current		± 20	mA
Iout	DC Output Current, per Pin		± 25	mA
ICC	DC Supply Current, VCC and GND Pins		± 75	mA
PD	Power Dissipation in Still Air,	SOIC Packages²	500	mW
		TSSOP Package²	450
Tstg	Storage Temperature		± 65 to + 150	_C

*Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute±maximum±rated conditions is not implied.

²Derating Ð SOIC Packages: ± 7 mW/ _C from 65_ to 125_C TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter		Min	Max	Unit
VCC	DC Supply Voltage		2.0	5.5	V
Vin	DC Input Voltage		0	5.5	V
Vout	DC Output Voltage		0	VCC	V
TA	Operating Temperature		± 40	+ 85	_C
tr, tf	Input Rise and Fall Time	VCC = 3.3V	0	100	ns/V
		VCC = 5.0V	0	20

DC ELECTRICAL CHARACTERISTICS

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

			VCC		TA = 25°C		TA = ± 40 to 85°C
Symbol	Parameter	Test Conditions	V	Min	Typ	Max	Min	Max	Unit
VIH	Minimum High±Level		2.0	1.50			1.50		V
	Input Voltage		3.0 to	VCC x 0.7			VCC x 0.7
			5.5
VIL	Maximum Low±Level		2.0			0.50		0.50	V
	Input Voltage		3.0 to			VCC x 0.3		VCC x 0.3
			5.5
VOH	Minimum High±Level	Vin = VIH or VIL	2.0	1.9	2.0		1.9		V
	Output Voltage	IOH = ± 50μA	3.0	2.9	3.0		2.9
			4.5	4.4	4.5		4.4
		Vin = VIH or VIL
		IOH = ± 4mA	3.0	2.58			2.48
		IOH = ± 8mA	4.5	3.94			3.80
VOL	Maximum Low±Level	Vin = VIH or VIL	2.0		0.0	0.1		0.1	V
	Output Voltage	IOL = 50μA	3.0		0.0	0.1		0.1
			4.5		0.0	0.1		0.1
		Vin = VIH or VIL
		IOL = 4mA	3.0			0.36		0.44
		IOL = 8mA	4.5			0.36		0.44
Iin	Maximum Input	Vin = 5.5 V or GND	0 to 5.5			± 0.1		± 1.0	μA
	Leakage Current

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MC74VHC573

DC ELECTRICAL CHARACTERISTICS

			VCC		TA = 25°C		TA = ± 40 to 85°C
Symbol	Parameter	Test Conditions	V	Min	Typ	Max	Min	Max	Unit
IOZ	Maximum Three±State	Vin = VIL or VIH	5.5			± 0.25		± 2.5	μA
	Leakage Current	Vout = VCC or GND
ICC	Maximum Quiescent	Vin = VCC or GND	5.5			4.0		40.0	μA
	Supply Current

AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)

							TA = 25°C				TA = ± 40 to 85°C
Symbol			Parameter	Test Conditions		Min	Typ		Max		Min	Max		Unit
tPLH,		Maximum Propagation Delay,		VCC = 3.3 ± 0.3V	CL = 15pF		7.6		11.9		1.0	14.0		ns
tPHL		LE to Q			CL = 50pF		10.1		15.4		1.0	17.5
				VCC = 5.0 ± 0.5V	CL = 15pF		5.0		7.7		1.0	9.0
					CL = 50pF		6.5		9.7		1.0	11.0
tPLH,		Maximum Propagation Delay,		VCC = 3.3 ± 0.3V	CL = 15pF		7.0		11.0		1.0	13.0		ns
tPHL		D to Q			CL = 50pF		9.5		14.5		1.0	16.5
				VCC = 5.0 ± 0.5V	CL = 15pF		4.5		6.8		1.0	8.0
					CL = 50pF		6.0		8.8		1.0	10.0
tPZL,		Output Enable Time,		VCC = 3.3 ± 0.3V	CL = 15pF		7.3		11.5		1.0	13.5		ns
tPZH		OE	to Q	RL = 1kΩ	CL = 50pF		9.8		15.0		1.0	17.0
				VCC = 5.0 ± 0.5V	CL = 15pF		5.2		7.7		1.0	9.0
				RL = 1kΩ	CL = 50pF		6.7		9.7		1.0	11.0
tPLZ,		Output Disable Time,		VCC = 3.3 ± 0.3V	CL = 50pF		10.7		14.5		1.0	16.5		ns
tPHZ		OE	to Q	RL = 1kΩ
				VCC = 5.0 ± 0.5V	CL = 50pF		6.7		9.7		1.0	11.0
				RL = 1kΩ
tOSLH,		Output to Output Skew		VCC = 3.3 ± 0.3V	CL = 50pF				1.5			1.5		ns
tOSHL				(Note 1.)
				VCC = 5.5 ± 0.5V	CL = 50pF				1.0			1.0		ns
				(Note 1.)
Cin		Maximum Input Capacitance					4		10			10		pF
Cout		Maximum Three±State					6							pF
		Output Capacitance (Output
		in High±Impedance State)
								Typical @ 25°C, VCC = 5.0V
CPD	Power Dissipation Capacitance (Note 2.)									29				pF

1.Parameter guaranteed by design. tOSLH = |tPLHm ± tPLHn|, tOSHL = |tPHLm ± tPHLn|.

2.CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.

Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 8 (per latch). CPD is used to determine the no±load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.

NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50 pF, VCC = 5.0V)

		TA = 25°C
Symbol	Parameter	Typ	Max	Unit
VOLP	Quiet Output Maximum Dynamic VOL	0.9	1.2	V
VOLV	Quiet Output Minimum Dynamic VOL	± 0.9	± 1.2	V
VIHD	Minimum High Level Dynamic Input Voltage		3.5	V
VILD	Maximum Low Level Dynamic Input Voltage		1.5	V

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