Fairchild Semiconductor HCPL-2630, HCPL-2611, HCPL-2601, 6N137, HCPL-2631 Datasheet

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					HIGH SPEED-10 MBit/s
					HIGH SPEED-10 MBit/s
					LOGIC GATE OPTOCOUPLERS


SINGLE-CHANNEL					DUAL-CHANNEL
6N137					HCPL-2630
HCPL-2601					HCPL-2631
HCPL-2611

DESCRIPTION

The 6N137, HCPL-2601/2611 single-channel and HCPL-2630/2631 dual-channel optocouplers consist of a 850 nm AlGaAS LED, optically coupled to a very high speed integrated photodetector logic gate with a strobable output. This output features an open collector, thereby permitting wired OR outputs. The coupled parameters are guaranteed over the temperature range of -40°C to +85°C. A maximum input signal of 5 mA will provide a minimum output sink current of 13 mA (fan out of 8).

An internal noise shield provides superior common mode rejection of typically 10 kV/µs. The HCPL2601 and HCPL2631 has a minimum CMR of 5 kV/µs.

The HCPL-2611 has a minimum CMR of 10 kV/µs.

FEATURES

•Very high speed-10 MBit/s

•Superior CMR-10 kV/µs

•Double working voltage-480V

•Fan-out of 8 over -40°C to +85°C

•Logic gate output

•Strobable output

•Wired OR-open collector

•U.L. recognized (File # E90700)

APPLICATIONS

•Ground loop elimination

•LSTTL to TTL, LSTTL or 5-volt CMOS

•Line receiver, data transmission

•Data multiplexing

•Switching power supplies

•Pulse transformer replacement

•Computer-peripheral interface

N/C 1		8	V
			CC
+	2	7	V
			E
V
F
_	3	6	V
			O
N/C 4		5	GND

6N137 HCPL-2601 HCPL-2611

	8
1		1
		1
+	1	8	V
			CC
V
F1
_	2	7	V
			01
_	3	6	V
			02
V
F2
+ 4		5	GND
	HCPL-2630
	HCPL-2631

TRUTH TABLE

(Positive Logic)

Input	Enable	Output

H	H	L

L	H	H

H	L	H

L	L	H

H	NC	L

L	NC	H

A 0.1 µF bypass capacitor must be connected between pins 8 and 5. (See note 1)

2001 Fairchild Semiconductor Corporation
DS300202	7/9/01	1 OF 11	www.fairchildsemi.com

HIGH SPEED-10 MBit/s

LOGIC GATE OPTOCOUPLERS

SINGLE-CHANNEL

DUAL-CHANNEL

6N137

HCPL-2630

HCPL-2601

HCPL-2631

HCPL-2611

ABSOLUTE MAXIMUM RATINGS (No derating required up to 85°C)

Parameter

Symbol

Value

Units

Storage Temperature

TSTG

-55 to +125

°C

Operating Temperature

TOPR

-40 to +85

°C

Lead Solder Temperature

TSOL

260 for 10 sec

°C

EMITTER

DC/Average Forward

Single channel

Input Current

Dual channel (Each channel)

Enable Input Voltage

Single channel

5.5

Not to exceed VCC by more than 500 mV

Reverse Input Voltage

Each channel

5.0

Power Dissipation

Single channel

100

Dual channel (Each channel)

DETECTOR

VCC

Supply Voltage

7.0

(1 minute max)

Output Current

Single channel

Dual channel (Each channel)

Output Voltage

Each channel

7.0

Collector Output

Single channel

Power Dissipation

Dual channel (Each channel)

RECOMMENDED OPERATING CONDITIONS

Parameter

Symbol

Min

Max

Units

Input Current, Low Level

IFL

250

µA

Input Current, High Level

IFH

*6.3

Supply Voltage, Output

VCC

4.5

5.5

Enable Voltage, Low Level

VEL

0.8

Enable Voltage, High Level

VEH

2.0

VCC

Low Level Supply Current

-40

+85

°C

Fan Out (TTL load)

* 6.3 mA is a guard banded value which allows for at least 20 % CTR degradation. Initial input current threshold value is 5.0 mA or less

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2 OF 11

7/9/01 DS300202

					HIGH SPEED-10 MBit/s
					HIGH SPEED-10 MBit/s
					LOGIC GATE OPTOCOUPLERS


SINGLE-CHANNEL					DUAL-CHANNEL
6N137					HCPL-2630
HCPL-2601					HCPL-2631
HCPL-2611

ELECTRICAL CHARACTERISTICS (TA = -40°C to +85°C Unless otherwise specified.)

INDIVIDUAL COMPONENT CHARACTERISTICS

Parameter

Test Conditions

Symbol

Min

Typ**

Max

Unit

EMITTER

(IF = 10 mA)

1.8

Input Forward Voltage

TA =25°C

1.4

1.75

Input Reverse Breakdown Voltage

(IR = 10 µA)

BVR

5.0

Input Capacitance

(VF = 0, f = 1 MHz)

CIN

Input Diode Temperature Coefficient

(IF = 10 mA)

VF/ TA

-1.4

mV/°C

DETECTOR

High Level Supply Current

Single Channel

(VCC = 5.5 V, IF = 0 mA)

ICCH

Dual Channel

(VE = 0.5 V)

Low Level Supply Current

Single Channel

(VCC = 5.5 V, IF = 10 mA)

ICCL

Dual Channel

(VE = 0.5 V)

Low Level Enable Current

(VCC = 5.5 V, VE = 0.5 V)

IEL

-0.8

-1.6

High Level Enable Current

(VCC = 5.5 V, VE = 2.0 V)

IEH

-0.6

-1.6

High Level Enable Voltage

(VCC = 5.5 V, IF = 10 mA)

VEH

2.0

Low Level Enable Voltage

(VCC = 5.5 V, IF = 10 mA) (Note 3)

VEL

0.8

SWITCHING CHARACTERISTICS (TA = -40°C to +85°C, VCC = 5 V, IF = 7.5 mA Unless otherwise specified.)

AC Characteristics

Test Conditions

Symbol

Min

Typ**

Max

Unit

Propagation Delay Time

(Note 4)

(TA =25°C)

TPLH

to Output High Level

(RL = 350 1, CL = 15 pF) (Fig. 12)

100

Propagation Delay Time

(Note 5)

(TA =25°C)

TPHL

to Output Low Level

(RL = 350 1, CL = 15 pF) (Fig. 12)

100

Pulse Width Distortion

(RL = 350 1, CL = 15 pF) (Fig. 12)

TPHL-TPLH

Output Rise Time (10-90%)

(RL = 350 1, CL = 15 pF)

(Note 6) (Fig. 12)

Output Fall Time (90-10%)

(RL = 350 1, CL = 15 pF)

(Note 7) (Fig. 12)

Enable Propagation Delay Time

(IF = 7.5 mA, VEH = 3.5 V)

tELH

to Output High Level

(RL = 350 1, CL = 15 pF) (Note 8) (Fig. 13)

Enable Propagation Delay Time

(IF = 7.5 mA, VEH = 3.5 V)

tEHL

to Output Low Level

(RL = 350 1, CL = 15 pF) (Note 9) (Fig. 13)

Common Mode Transient Immunity (TA =25°C) VCM = 50 V, (Peak)

(at Output High Level)

(IF = 0 mA, VOH (Min.) = 2.0 V)

CMH

V/µs

6N137, HCPL-2630

(RL = 350 1) (Note 10)

10,000

HCPL-2601, HCPL-2631

(Fig. 14)

5000

10,000

HCPL-2611

VCM = 400 V

10,000

15,000

(RL = 350 1) (IF = 7.5 mA, VOL (Max.) = 0.8 V)

10,000

Common Mode

6N137, HCPL-2630

VCM = 50 V (Peak)

CML

V/µs

Transient Immunity

HCPL-2601, HCPL-2631

(TA =25°C)

5000

10,000

(at Output Low Level)

(Note 11) (Fig. 14)

HCPL-2611

(TA =25°C)

VCM = 400 V

10,000

15,000

DS300202

7/9/01

3 OF 11

www.fairchildsemi.com

					HIGH SPEED-10 MBit/s
					HIGH SPEED-10 MBit/s
					LOGIC GATE OPTOCOUPLERS


SINGLE-CHANNEL					DUAL-CHANNEL
6N137					HCPL-2630
HCPL-2601					HCPL-2631
HCPL-2611

TRANSFER CHARACTERISTICS (TA = -40°C to +85°C Unless otherwise specified.)

DC Characteristics	Test Conditions	Symbol	Min	Typ**	Max	Unit

High Level Output Current	(VCC = 5.5 V, VO = 5.5 V)	IOH			100	µA
(IF = 250 µA, VE = 2.0 V) (Note 2)		IOH			100	µA
(IF = 250 µA, VE = 2.0 V) (Note 2)
Low Level Output Current	(VCC = 5.5 V, IF = 5 mA)	VOL		.35	0.6	V
(VE = 2.0 V, ICL = 13 mA) (Note 2)		VOL		.35	0.6	V
(VE = 2.0 V, ICL = 13 mA) (Note 2)
Input Threshold Current	(VCC = 5.5 V, VO = 0.6 V,	IFT		3	5	mA
Input Threshold Current	VE = 2.0 V, IOL = 13 mA)	IFT		3	5	mA
	VE = 2.0 V, IOL = 13 mA)

ISOLATION CHARACTERISTICS (TA = -40°C to +85°C Unless otherwise specified.)

Characteristics	Test Conditions	Symbol	Min	Typ**	Max	Unit

Input-Output	(Relative humidity = 45%)
Insulation Leakage Current	(TA = 25°C, t = 5 s)	II-O			1.0*	µA
	(VI-O = 3000 VDC)	II-O			1.0*	µA
	(VI-O = 3000 VDC)
	(Note 12)

Withstand Insulation Test Voltage	(RH < 50%, TA = 25°C)	VISO	2500			VRMS
	(Note 12) ( t = 1 min.)	VISO	2500			VRMS
	(Note 12) ( t = 1 min.)

Resistance (Input to Output)	(VI-O = 500 V) (Note 12)	RI-O		1012		1
Capacitance (Input to Output)	(f = 1 MHz) (Note 12)	CI-O		0.6		pF

** All typical values are at VCC = 5 V, TA = 25°C

NOTES

1.The VCC supply to each optoisolator must be bypassed by a 0.1µF capacitor or larger. This can be either a ceramic or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible to the package VCC and GND pins of each device.

2.Each channel.

3.Enable Input - No pull up resistor required as the device has an internal pull up resistor.

4.tPLH - Propagation delay is measured from the 3.75 mA level on the HIGH to LOW transition of the input current pulse to the 1.5 V level on the LOW to HIGH transition of the output voltage pulse.

5.tPHL - Propagation delay is measured from the 3.75 mA level on the LOW to HIGH transition of the input current pulse to the 1.5 V level on the HIGH to LOW transition of the output voltage pulse.

6.tr - Rise time is measured from the 90% to the 10% levels on the LOW to HIGH transition of the output pulse.

7.tf - Fall time is measured from the 10% to the 90% levels on the HIGH to LOW transition of the output pulse.

8.tELH - Enable input propagation delay is measured from the 1.5 V level on the HIGH to LOW transition of the input voltage pulse to the 1.5 V level on the LOW to HIGH transition of the output voltage pulse.

9.tEHL - Enable input propagation delay is measured from the 1.5 V level on the LOW to HIGH transition of the input voltage pulse to the 1.5 V level on the HIGH to LOW transition of the output voltage pulse.

10.CMH - The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the high state (i.e., VOUT > 2.0 V). Measured in volts per microsecond (V/µs).

11.CML - The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the low output state (i.e., VOUT < 0.8 V). Measured in volts per microsecond (V/µs).

12.Device considered a two-terminal device: Pins 1,2,3 and 4 shorted together, and Pins 5,6,7 and 8 shorted together.

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7/9/01 DS300202

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