May 1999
Revised September 1999
GTLP18T612
18-Bit LVTTL/GTLP Universal Bus Transceiver
General Description
The GTLP18T612 is an 18-bit universal bus transceiver which provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data transfer. The device provides a high speed interface for cards operating at LVTTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP’s reduced output swing (< 1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transistor logic (GTL) JEDEC standard JESD8-3.
Fairchild's GTLP has internal edge-rate control and is Process, Voltage, and Temperature (PVT) compensated. Its function is similar to BTL or GTL but with different output levels and receiver thresholds. GTLP output LOW level is less than 0.5V, the output HIGH is 1.5V and the receiver threshold is 1.0V.
Features
■Bidirectional interface between GTLP and LVTTL logic levels
■Edge Rate Control to minimize noise on the GTLP port
■Power up/down high impedance for live insertion
■External VREF pin for receiver threshold
■BiCMOS technology for low power dissipation
■Bushold data inputs on A Port eliminates the need for external pull-up resistors for unused inputs
■LVTTL compatible Driver and Control inputs
■Flow-through architecture optimizes PCB layout
■Open drain on GTLP to support wired-or connection
■A-Port source/sink −24 mA/+24 mA
■B-Port sink capability +50 mA
■D-type flip-flop, latch and transparent data paths
Ordering Code:
Order Number |
Package Number |
Package Description |
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GTLP18T612MEA |
MS56A |
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide |
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GTLP18T612MTD |
MTD56 |
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide |
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Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Transceiver Bus Universal LVTTL/GTLP Bit-18 GTLP18T612
© 1999 Fairchild Semiconductor Corporation |
DS500169 |
www.fairchildsemi.com |
GTLP18T612
Pin Descriptions |
Connection Diagram |
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Pin Names |
Description |
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A-to-B Output Enable |
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OEAB |
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(Active LOW) (LVTTL Level) |
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B-to-A Output Enable |
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OEBA |
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(Active LOW) (LVTTL Level) |
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A-to-B Clock/LE Enable |
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CEAB |
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(Active LOW) (LVTTL Level) |
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B-to-A Clock/LE Enable |
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CEBA |
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(Active LOW) (LVTTL Level) |
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LEAB |
A-to-B Latch Enable |
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(Transparent HIGH) (LVTTL Level) |
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LEBA |
B-to-A Latch Enable |
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(Transparent HIGH) (LVTTL Level) |
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VREF |
GTLP Input Threshold |
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Reference Voltage |
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CLKAB |
A-to-B Clock (LVTTL Level) |
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CLKBA |
B-to-A Clock (LVTTL Level) |
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A1–A18 |
A-to-B Data Inputs or |
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B-to-A 3-STATE Outputs |
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B1–B18 |
B-to-A Data Inputs or |
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A-to-B Open Drain Outputs |
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Functional Description
The GTLP18T612 is an 18 bit registered transceiver containing D-type flip-flop, latch and transparent modes of operation for the data path. Data flow in each direction is controlled by the clock enables (CEAB and CEBA), latch enables (LEAB and LEBA), clock (CLKAB and CLKBA) and output enables (OEAB and OEBA). The clock enables (CEAB and CEBA) and the output enables (OEAB and OEBA) control the 18 bits of data for the A-to-B and B-to-A directions respectively.
For A-to-B data flow, when CEAB is LOW, the device operates on the LOW-to-HIGH transition of CLKAB for the flip-flop and on the HIGH-to-LOW transition of LEAB for the latch path. That is, if CEAB is LOW and LEAB is LOW the A data is latched regardless as to the state of CLKAB (HIGH or LOW) and if LEAB is HIGH the device is in transparent mode. When OEAB is LOW the outputs are active. When OEAB is HIGH the outputs are HIGH impedance. The data flow of B-to-A is similar except that CEBA, OEBA, LEBA, and CLKBA are used.
www.fairchildsemi.com |
2 |
Truth Table (Note 1)
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Inputs |
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Output |
Mode |
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B |
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CEAB |
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OEAB |
LEAB |
CLKAB |
A |
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X |
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H |
X |
X |
X |
Z |
Latched |
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L |
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L |
L |
H or L |
X |
B0 (Note 2) |
storage |
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L |
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L |
L |
H or L |
X |
B0 (Note 3) |
of A data |
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X |
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L |
H |
X |
L |
L |
Transparent |
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X |
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L |
H |
X |
H |
H |
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L |
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L |
L |
− |
L |
L |
Clocked |
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L |
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L |
L |
− |
H |
H |
storage |
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of A data |
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H |
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L |
L |
X |
X |
B0 (Note 3) |
Clock inhibit |
Note 1: A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA, and CEBA.
Note 2: Output level before the indicated steady state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW.
Note 3: Output level before the indicated steady-state input conditions were established.
Logic Diagram
GTLP18T612
3 |
www.fairchildsemi.com |
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