June 1997
Revised October 1998
GTLP16616
17-Bit TTL/GTLP Bus Transceiver with Buffered Clock
General Description
The GTLP16616 is a 17-bit registered bus transceiver that provides TTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data flow and provides a buffered GTLP (CLKOUT) clock output from the TTL CLKAB. The device provides a high speed interface between cards operating at TTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP’s reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transceiver logic (GTL) JEDEC standard JESD8-3.
Fairchild’s GTLP has internal edge-rate control and is process, voltage, and temperature (PVT) compensated. Its function is similar to BTL and GTL but with different output levels and receiver threshold. GTLP output LOW level is typically less than 0.5V, the output level HIGH is 1.5V and the receiver threshold is 1.0V.
Features
■Bidirectional interface between GTLP and TTL logic levels
■Edge Rate Control to minimize noise on the GTLP port
■Power up/down/off high impedance for live insertion
■External VREF pin for receiver threshold
■CMOS technology for low power dissipation
■5 V tolerant inputs and outputs on the A-Port
■Bus-hold data inputs on the A-Port eliminates the need for external pull-up resistors on unused inputs.
■TTL compatible driver and control inputs
■Flow through pinout optimizes PCB layout
■Open drain on GTLP to support wired-or connection
■A-port source/sink −32 mA/+32 mA
■D-type flip-flop, latch and transparent data paths
■GTLP Buffered CLKAB signal available (CLKOUT)
■Recommended Operating Temperature −40°C to 85°C
Ordering Code:
Order Number |
Package Number |
Package Description |
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GTLP16616MEA |
MS56A |
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118 0.300” Wide |
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GTLP16616MTD |
MTD56 |
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide |
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Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Clock Buffered with Transceiver Bus TTL/GTLP Bit-17 GTLP16616
© 1998 Fairchild Semiconductor Corporation |
DS500017.prf |
www.fairchildsemi.com |
GTLP16616
Pin Descriptions |
Connection Diagram |
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Pin Names |
Description |
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A-to-B Output Enable (Active LOW) |
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OEAB |
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B-to-A Output Enable (Active LOW) |
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OEBA |
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A-to-B Clock Enable (Active LOW) |
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CEAB |
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B-to-A Clock Enable (Active LOW) |
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CEBA |
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LEAB |
A-to-B Latch Enable (Transparent HIGH) |
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LEBA |
B-to-A Latch Enable (Transparent HIGH) |
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VREF |
GTLP Reference Voltage |
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CLKAB |
A-to-B Clock |
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CLKBA |
B-to-A Clock |
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A1-A17 |
A-to-B Data Inputs or B-to-A 3-STATE |
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Outputs |
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B1-B17 |
B-to-A Data Inputs or |
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A-to-B Open Drain Outputs |
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CLKIN |
B-to-A Buffered Clock Output |
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CLKOUT |
GTLP Buffered Clock Output of CLKAB |
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Functional Description
The GTLP16616 is a 17 bit registered transceiver containing D-type flip-flop, latch and transparent modes of operation for the data path and a GTLP translation of the CLKAB signal (CLKOUT). Data flow in each direction is controlled by the clock enables (CEAB and CEBA), latch enables (LEAB and LEBA), clock (CLKAB and CLKBA) and output enables (OEAB and OEBA). The clock enables (CEAB and CEBA) enable all 17 bits. The output enables (OEAB and OEBA) control both the 17 bits of data and the CLKOUT/CLKIN buffered clock path.
For A-to-B data flow, when CEAB is LOW, the device operates on the LOW-to-HIGH transition of CLKAB for the flip-flop and on the HIGH-to-LOW transition of LEAB for the latch path. That is, if CEAB is LOW and LEAB is LOW the A data is latched regardless as to the state of CLKAB (HIGH or LOW) and if LEAB is HIGH the device is in transparent mode. When OEAB is LOW the outputs are active. When OEAB is HIGH the outputs are HIGH impedance. The data flow of B-to-A is similar except that CEBA, OEBA, LEBA and CLKBA are used.
Truth Table
(Note 1)
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Inputs |
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Output |
Mode |
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B |
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CEAB |
OEAB |
LEAB |
CLKAB |
A |
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X |
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H |
X |
X |
X |
Z |
Latched |
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L |
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L |
L |
H or L |
X |
B0 (Note 2) |
storage |
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L |
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L |
L |
H or L |
X |
B0 (Note 3) |
of A data |
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X |
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L |
H |
X |
L |
L |
Transparent |
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X |
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L |
H |
X |
H |
H |
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L |
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L |
L |
− |
L |
L |
Clocked storage |
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L |
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L |
L |
− |
H |
H |
of A data |
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H |
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L |
L |
X |
X |
B0 (Note 3) |
Clock inhibit |
Note 1: A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA, and CEBA.
Note 2: Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH prior to LEAB going LOW.
Note 3: Output level before the indicated steady-state input conditions were established.
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2 |
Logic Diagram
GTLP16616
3 |
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