August 1998
Revised August 1999
GTLP6C816A
LVTTL-to-GTLP Clock Driver
General Description
The GTLP6C816A is a clock driver that provides LVTTL to GTLP signal level translation (and vice versa). The device provides a high speed interface between cards operating at LVTTL logic levels and a backplane operating at GTL(P) logic levels. High speed backplane operation is a direct result of GTL(P)’s reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transceiver logic (GTL) JEDEC standard JESD8-3.
Fairchild’s GTL(P) has internal edge-rate control and is process, voltage, and temperature (PVT) compensated. Its function is similar to BTL and GTL but with different output levels and receiver threshold. GTLP output LOW level is typically less than 0.5V, the output level HIGH is 1.5V and the receiver threshold is 1.0V.
Features
■Interface between LVTTL and GTLP logic levels
■Edge Rate Control to minimize noise on the GTLP port
■Power up/down high impedance for live insertion
■1:6 fanout clock driver for LVTTL port
■1:2 fanout clock driver for GTLP port
■LVTTL compatible driver and control inputs
■Flow through pinout optimizes PCB layout
■Open drain on GTLP to support wired-or connection
■A Port source/sink −24/+24 mA
■B Port sink 50 mA
■−40°C to +85°C temperature capability
■Low voltage version of GTLP6C816
Ordering Code:
Order Number |
Package Number |
Package Description |
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GTLP6C816AMTC |
MTC24 |
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide |
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Pin Descriptions |
Connection Diagram |
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Pin Names |
Description |
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TTLIN, GTLPIN |
Clock Inputs |
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(LVTTL and GTLP respectively) |
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Output Enable (Active LOW) |
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OEB |
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GTLP Port (LVTTL Levels) |
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Output Enable (Active LOW) |
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OEA |
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TTL Port (LVTTL Levels) |
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VCCT.GNDT |
TTL Output Supplies |
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VCC |
Internal Circuitry VCC |
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GNDG |
OBn GTLP Output Grounds |
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VREF |
Voltage Reference Input |
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OA0–OA5 |
TTL Buffered Clock Outputs |
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OB0–OB1 |
GTLP Buffered Clock Outputs |
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Driver Clock GTLP-to-LVTTL GTLP6C816A
© 1999 Fairchild Semiconductor Corporation |
DS500179 |
www.fairchildsemi.com |
GTLP6C816A
Functional Description
The GTLP6C816A is a clock driver providing LVTTL-to-GTLP clock translation, and GTLP-to-LVTTL clock translation in the same package. The LVTTL-to-GTLP direction is a 1:2 clock driver path with a single Enable pin (OEB). For the GTLP-to- LVTTL direction the clock receiver path is a 1:6 buffer with a single Enable control (OEA). Data polarity is inverting for both directions.
Truth Tables
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Inputs |
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Outputs |
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TTLIN |
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OEB |
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OBn |
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H |
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L |
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L |
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L |
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L |
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H |
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X |
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H |
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High Z |
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Inputs |
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Outputs |
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GTLPIN |
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OEA |
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OAn |
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H |
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L |
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L |
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L |
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L |
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H |
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X |
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H |
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High Z |
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Logic Diagram
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) |
−0.5V to +4.6V |
DC Input Voltage (VI) |
−0.5V to +4.6V |
DC Output Voltage (VO) |
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Outputs 3-STATE |
−0.5V to +4.6V |
Outputs Active (Note 2) |
−0.5V to +4.6V |
DC Output Sink Current into |
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OA-Port IOL |
48 mA |
DC Output Source Current |
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from OA-Port IOH |
−48 mA |
DC Output Sink Current into |
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OB-Port in the LOW State IOL |
100 mA |
DC Input Diode Current (IIK) |
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VI < 0V |
−50 mA |
DC Output Diode Current (IOK) |
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VO < 0V |
−50 mA |
VO > VCC |
+50 mA |
ESD Rating |
> 2000V |
Storage Temperature (TSTG) |
−65°C to +150°C |
Recommended Operating
Conditions (Note 3)
Supply Voltage VCC |
3.15V to 3.45V |
Bus Termination Voltage (VTT) |
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GTLP |
1.47V to 1.53V |
GTL |
1.14V to 1.26V |
VREF |
0.98V to 1.02V |
Input Voltage (VI) on INA-Port |
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and Control Pins |
0.0V to 3.45V |
HIGH Level Output Current (IOH) |
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OA-Port |
−24 mA |
LOW Level Output Current (IOL) |
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OA-Port |
+24 mA |
OB-Port |
+50 mA |
Operating Temperature (TA) |
−40°C to +85°C |
Note 1: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 2: Io Absolute Maximum Rating must be observed.
Note 3: Unused inputs must be held High or Low.
GTLP6C816A
3 |
www.fairchildsemi.com |
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