July 1997
Revised December 1999
FST16232
Synchronous 16-Bit to 32-Bit
Multiplexer/Demultiplexer Bus Switch
General Description
The Fairchild Switch FST16232 is a 16-bit to 32-bit highspeed CMOS TTL-compatible synchronous multiplexer/ demultiplexer bus switch. The low on resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise.
The device allows two separate datapaths to be multiplexed onto, or demultiplexed from, a single path. Two control select pins (S1, S0) are synchronous and clocked on
the rising edge of CLK when CLKEN is LOW.
Features
■4Ω switch connection between two ports.
■Minimal propagation delay through the switch.
■Low lCC.
■Zero bounce in flow-through mode.
■Control inputs compatible with TTL level.
Ordering Code:
Order Number |
Package Number |
Package Description |
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FST16232MEA |
MS56A |
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide |
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FST16232MTD |
MTD56 |
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide |
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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Diagram
Switch Bus Multiplexer/Demultiplexer Bit-32 to Bit-16 Synchronous FST16232
© 1999 Fairchild Semiconductor Corporation |
DS500054 |
www.fairchildsemi.com |
FST16232
Connection Diagram
Pin Descriptions
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Description |
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S1, S0 |
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Control Pins |
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CLK |
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Clock Input |
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Clock Enable Input |
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CLKEN |
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1A, 2A |
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Bus A |
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1B, 2B |
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Bus B |
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Truth Table |
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Inputs |
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Function |
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S1 |
S0 |
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CLK |
CLKEN |
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X |
X |
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X |
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H |
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Last State |
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L |
L |
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↑ |
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L |
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Disconnect |
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L |
H |
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↑ |
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L |
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A = B1 and A = B2 |
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H |
L |
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↑ |
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L |
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A = B1 |
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H |
H |
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↑ |
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L |
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A = B2 |
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www.fairchildsemi.com |
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