Fairchild Semiconductor 74ACQ573SJX, 74ACQ573SJ, 74ACQ573SCX, 74ACQ573SC, 74ACQ573PC Datasheet
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January 1990
Revised November 1999
74ACQ573 • 74ACTQ573
Quiet Series Octal Latch with 3-STATE Outputs
General Description
The ACQ/ACTQ573 is a high-speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. The ACQ/ACTQ573 is functionally identical to the ACQ/ACTQ373 but with inputs and outputs on opposite sides of the package. The ACQ/ACTQ utilizes Fairchild’s Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector in addition to a split ground bus for superior performance.
Features
■ICC and IOZ reduced by 50%
■Guaranteed simultaneous switching noise level and dynamic threshold performance
■Guaranteed pin-to-pin skew AC performance
■Improved latch-up immunity
■Inputs and outputs on opposite sides of package allow easy interface with microprocessors
■Outputs source/sink 24 mA
Ordering Code:
Order Number |
Package Number |
Package Description |
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74ACQ573SC |
M20B |
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body |
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74ACQ573SJ |
M20D |
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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74ACQ573MTC |
MTC20 |
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide |
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74ACQ573PC |
N20A |
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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74ACTQ573SC |
M20B |
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body |
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74ACTQ573SJ |
M20D |
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide |
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74ACTQ573QSC |
MQA20 |
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150” Wide |
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74ACTQ573PC |
N20A |
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide |
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Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols |
Connection Diagram |
IEEE/IEC |
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Pin Descriptions |
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Pin Names |
Description |
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D0–D7 |
Data Inputs |
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LE |
Latch Enable Input |
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3-STATE Output Enable Input |
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OE |
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O0–O7 |
3-STATE Latch Outputs |
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FACT , Quiet Series , FACT Quiet Series , and GTO are trademarks of Fairchild Semiconductor Corporation
Outputs STATE-3 with Latch Octal Series Quiet 74ACTQ573 • 74ACQ573
© 1999 Fairchild Semiconductor Corporation |
DS010633 |
www.fairchildsemi.com |
74ACQ573 • 74ACTQ573
Functional Description
The ACQ/ACTQ573 contains eight D-type latches with 3- STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D-type input changes. When LE is LOW the latches store the information that was present on the D-type inputs at setup time preceding the HIGH-to- LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are enabled. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches.
Logic Diagram
Truth Table
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Inputs |
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Outputs |
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OE |
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LE |
D |
On |
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L |
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H |
H |
H |
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L |
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H |
L |
L |
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L |
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L |
X |
O0 |
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H |
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X |
X |
Z |
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H = |
HIGH Voltage |
L = |
LOW Voltage |
Z = |
High Impedance |
X = |
Immaterial |
O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com |
2 |
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) |
− 0.5V to + 7.0V |
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DC Input Diode Current (IIK) |
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VI = |
− 0.5V |
− 20 mA |
VI = |
VCC + 0.5V |
+ 20 mA |
DC Input Voltage (VI) |
− 0.5V to VCC + 0.5V |
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DC Output Diode Current (IOK) |
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VO = |
− 0.5V |
− 20 mA |
VO = |
VCC + 0.5V |
+ 20 mA |
DC Output Voltage (VO) |
− 0.5V to VCC + 0.5V |
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DC Output Source |
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or Sink Current (IO) |
± 50 mA |
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DC VCC or Ground Current |
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per Output Pin (ICC or IGND) |
± 50 mA |
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Storage Temperature (TSTG) |
− 65° C to + 150° C |
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DC Latchup Source |
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or Sink Current |
± 300 mA |
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Junction Temperature (TJ |
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PDIP |
140° C |
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Recommended Operating
Conditions
Supply Voltage (VCC) |
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ACQ |
2.0V to 6.0V |
ACTQ |
4.5V to 5.5V |
Input Voltage (VI) |
0V to VCC |
Output Voltage (VO) |
0V to VCC |
Operating Temperature (TA) |
− 40° C to + 85° C |
Minimum Input Edge Rate ∆ V/∆ t |
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ACQ Devices |
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VIN from 30% to 70% of VCC |
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VCC @ 3.0V, 4.5V, 5.5V |
125 mV/ns |
Minimum Input Edge Rate ∆ V/∆ t |
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ACTQ Devices |
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VIN from 0.8V to 2.0V |
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VCC @ 4.5V, 5.5V |
125 mV/ns |
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics for ACQ
Symbol |
Parameter |
VCC |
TA = + 25° C |
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TA = − 40° C to + 85° C |
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Conditions |
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(V) |
Typ |
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Guaranteed Limits |
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VIH |
Minimum HIGH Level |
3.0 |
1.5 |
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2.1 |
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2.1 |
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VOUT = |
0.1V |
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Input Voltage |
4.5 |
2.25 |
3.15 |
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3.15 |
V |
or VCC − |
0.1V |
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5.5 |
2.75 |
3.85 |
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3.85 |
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VIL |
Maximum LOW Level |
3.0 |
1.5 |
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0.9 |
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0.9 |
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VOUT = |
0.1V |
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Input Voltage |
4.5 |
2.25 |
1.35 |
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1.35 |
V |
or VCC − |
0.1V |
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5.5 |
2.75 |
1.65 |
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1.65 |
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VOH |
Minimum HIGH Level |
3.0 |
2.99 |
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2.9 |
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2.9 |
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Output Voltage |
4.5 |
4.49 |
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4.4 |
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4.4 |
V |
IOUT = |
− |
50 µ A |
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5.5 |
5.49 |
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5.4 |
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5.4 |
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VIN = |
VIL or VIH |
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3.0 |
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2.56 |
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2.46 |
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IOH = |
− |
12 mA |
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4.5 |
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3.86 |
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3.76 |
V |
IOH = |
− |
24 mA |
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5.5 |
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4.86 |
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4.76 |
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IOH = |
− 24 mA (Note 2) |
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VOL |
Maximum LOW Level |
3.0 |
0.002 |
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0.1 |
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0.1 |
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Output Voltage |
4.5 |
0.001 |
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0.1 |
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0.1 |
V |
IOUT = |
50 µ A |
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5.5 |
0.001 |
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0.1 |
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0.1 |
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VIN = |
VIL or VIH |
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3.0 |
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0.36 |
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0.44 |
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IOL = |
12 mA |
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4.5 |
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0.36 |
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0.44 |
V |
IOL = |
24 mA |
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5.5 |
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0.36 |
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0.44 |
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IOL = |
24 mA (Note 2) |
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IIN (Note 4) |
Maximum Input Leakage Current |
5.5 |
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± |
0.1 |
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± 1.0 |
µ A |
VI = |
VCC, GND |
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IOLD |
Minimum Dynamic |
5.5 |
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75 |
mA |
VOLD = |
1.65 VMax |
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IOHD |
Output Current (Note 3) |
5.5 |
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− 75 |
mA |
VOHD = |
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3.85 VMin |
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ICC (Note 4) |
Maximum Quiescent Supply Current |
5.5 |
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4.0 |
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40.0 |
µ A |
VIN = |
VCC or GND |
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IOZ |
Maximum 3-STATE |
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VI (OE) = VIL, VIH |
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Leakage Current |
5.5 |
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± |
0.25 |
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± 2.5 |
µ A |
VI = |
VCC, GND |
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VO = |
VCC, GND |
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VOLP |
Quiet Output |
5.0 |
1.1 |
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1.5 |
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V |
Figure 1, Figure 2 |
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Maximum Dynamic VOL |
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(Note 5)(Note 6) |
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74ACTQ573 • 74ACQ573
3 |
www.fairchildsemi.com |
74ACQ573 • 74ACTQ573
DC Electrical Characteristics for ACQ (Continued)
Symbol |
Parameter |
VCC |
TA = + 25° C |
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TA = − 40° C to + 85° C |
Units |
Conditions |
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(V) |
Typ |
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Guaranteed Limits |
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VOLV |
Quiet Output |
5.0 |
− 0.6 |
− 1.2 |
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V |
Figure 1, Figure 2 |
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Minimum Dynamic VOL |
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(Note 5)(Note 6) |
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VIHD |
Minimum HIGH Level |
5.0 |
3.1 |
3.5 |
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V |
(Note 5)(Note 7) |
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Dynamic Input Voltage |
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VILD |
Maximum LOW Level |
5.0 |
1.9 |
1.5 |
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V |
(Note 5)(Note 7) |
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Dynamic Input Voltage |
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Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
Note 5: Plastic DIP package.
Note 6: Max number of outputs defined as (n). Data Inputs are driven 0V to 5V. One output @ GND.
Note 7: Max number of Data Inputs (n) switching. (n − 1) Inputs switching 0V to 5V (ACQ). Input-under-test switching: 5V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz.
DC Electrical Characteristics for ACTQ
Symbol |
Parameter |
VCC |
TA = + 25° C |
TA = − 40° C to + 85° C |
Units |
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Conditions |
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(V) |
Typ |
Guaranteed Limits |
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VIH |
Minimum HIGH Level |
4.5 |
1.5 |
2.0 |
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2.0 |
V |
VOUT = |
0.1V |
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Input Voltage |
5.5 |
1.5 |
2.0 |
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2.0 |
or VCC − |
0.1V |
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VIL |
Maximum LOW Level |
4.5 |
1.5 |
0.8 |
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0.8 |
V |
VOUT = |
0.1V |
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Input Voltage |
5.5 |
1.5 |
0.8 |
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0.8 |
or VCC − |
0.1V |
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VOH |
Minimum HIGH Level |
4.5 |
4.49 |
4.4 |
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4.4 |
V |
IOUT = |
− |
50 µ A |
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Output Voltage |
5.5 |
5.49 |
5.4 |
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5.4 |
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VIN = |
VIL or VIH |
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4.5 |
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3.86 |
3.76 |
V |
IOH = |
− |
24 mA |
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5.5 |
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4.86 |
4.76 |
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IOH = |
− 24 mA (Note 8) |
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VOL |
Maximum LOW Level |
4.5 |
0.001 |
0.1 |
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0.1 |
V |
IOUT = |
50 µ A |
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Output Voltage |
5.5 |
0.001 |
0.1 |
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0.1 |
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VIN = |
VIL or VIH |
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4.5 |
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0.36 |
0.44 |
V |
IOL = |
24 mA |
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5.5 |
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0.36 |
0.44 |
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IOL = |
24 mA (Note 8) |
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IIN |
Maximum Input |
5.5 |
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± 0.1 |
± |
1.0 |
µ A |
VI = |
VCC, GND |
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Leakage Current |
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IOZ |
Maximum 3-STATE |
5.5 |
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± 0.25 |
± |
2.5 |
µ A |
VI = |
VIL, VIH |
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Leakage Current |
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VO = |
VCC, GND |
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ICCT |
Maximum ICC/Input |
5.5 |
0.6 |
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1.5 |
mA |
VI = |
VCC − 2.1V |
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IOLD |
Minimum Dynamic |
5.5 |
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75 |
mA |
VOLD = |
1.65V Max |
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IOHD |
Output Current (Note 9) |
5.5 |
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− 75 |
mA |
VOHD = |
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3.85V Min |
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ICC |
Maximum Quiescent Supply Current |
5.5 |
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4.0 |
40.0 |
µ A |
VIN = |
VCC or GND |
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VOLP |
Quiet Output |
5.0 |
1.1 |
1.5 |
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V |
Figure 1, Figure 2 |
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Maximum Dynamic VOL |
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(Note 10)(Note 11) |
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VOLV |
Quiet Output |
5.0 |
− 0.6 |
− 1.2 |
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V |
Figure 1, Figure 2 |
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Minimum Dynamic VOL |
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(Note 10)(Note 11) |
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VIHD |
Minimum HIGH Level |
5.0 |
1.9 |
2.2 |
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V |
(Note 10)(Note 12) |
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Dynamic Input Voltage |
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VILD |
Maximum LOW Level |
5.0 |
1.2 |
0.8 |
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V |
(Note 10)(Note 12) |
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Dynamic Input Voltage |
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Note 8: All outputs loaded; thresholds on input associated with output under test.
Note 9: Maximum test duration 2.0 ms, one output loaded at a time.
Note 10: Plastic DIP package.
Note 11: Max number of outputs defined as (n). Data Inputs are driven 0V to 3V. One output @ GND.
Note 12: Max number of data inputs (n) switching. (n − 1) inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz.
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4 |
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