White Electronic Designs WF128K32N-90H1Q5A, WF128K32N-90H1Q5, WF128K32N-90H1M5A, WF128K32N-90H1M5, WF128K32N-90H1I5A Datasheet

WF128K32-XXX5

128KX32 5V FLASH MODULE, SMD 5962-94716

FEATURES

νAccess Times of 50*, 60, 70, 90, 120, 150ns

νPackaging:

•66 pin, PGA Type, 1.075 inch square, Hermetic Ceramic HIP (Package 400)

•68 lead, Hermetic CQFP (G2U)1, 22.4mm (0.880 inch) square, 3.56mm (0.140 inch) high (Package 510)

•68 lead, Hermetic CQFP (G1U), 23.9mm (0.940 inch) square, 3.56mm (0.140 inch) high (Package 519)

•68 lead, Hermetic CQFP (G1T), 23.9mm (0.940 inch) square, 4.06mm (0.160 inch) high (Package 524)

νSector Architecture

•8 equal size sectors of 16KBytes each

•Any combination of sectors can be concurrently erased.

Also supports full chip erase

ν100,000 Erase/Program Cycles Typical, 0°C to +70°C

νOrganized as 128Kx32

νCommercial, Industrial and Military Temperature Ranges

ν5 Volt Programming. 5V ± 10% Supply

νLow Power CMOS, 1mA Standby Typical

νEmbedded Erase and Program Algorithms

νTTL Compatible Inputs and CMOS Outputs

νBuilt-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation

νPage Program Operation and Internal Program Control Time

νWeight

WF128K32-XG1UX5 - 5 grams typical

WF128K32-XG1TX5 - 5 grams typical

WF128K32-XG2UX51 - 8 grams typical

WF128K32-XH1X5 - 13 grams typical

Note 1: Package Not Recommended For New Design

Note: For programming information refer to Flash Programming 1M5 Application Note.

* The access time of 50ns is available in Industrial and Commercial temperature ranges only.

FIG. 1 PIN CONFIGURATION FOR WF128K32N-XH1X5

TOP VIEW	PIN DESCRIPTION
	I/O0-31	DataInputs/Outputs
	A0-16	AddressInputs
	WE1-4	Write Enables
	CS1-4	Chip Selects
	OE	OutputEnable
	VCC	Power Supply
	GND	Ground
	NC	Not Connected

BLOCK DIAGRAM

December 2001 Rev. 4

1

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WF128K32-XXX5

FIG. 3 PIN CONFIGURATION FOR WF128K32-XG1UX5, WF128K32-XG1TX5 AND WF128K32-XG2UX51

TOP VIEW

PIN DESCRIPTION

NC

A0

A1

A2

A3

A4

A5

CS3

GND

CS4 WE1

A6

A7

A8

A9

A10

VCC

I/O0-31

DataInputs/Outputs

9

8

7

6

5

4

3

2

1

68 67 66 65 64 63 62 61

A0-16

AddressInputs

I/O0

10

60

I/O16

WE1-4

Write Enables

I/O1

11

59

I/O17

I/O2

12

58

I/O18

1-4

Chip Selects

CS

I/O3

13

57

I/O19

I/O4

14

56

I/O20

OE

OutputEnable

I/O5

15

55

I/O21

VCC

Power Supply

I/O6

16

54

I/O22

I/O7

17

53

I/O23

GND

Ground

GND

18

52

GND

I/O8

19

51

I/O24

NC

Not Connected

I/O9

20

50

I/O25

I/O10

21

49

I/O26

BLOCK DIAGRAM

I/O11

22

48

I/O27

I/O12

23

47

I/O28

I/O13

24

46

I/O29

I/O14

25

45

I/O30

I/O15

26

44

I/O31

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

VCC

A11

A12

A13

A14

A15

A16

CS1

OE

CS2 NC

E2

E3

E4

NC

NC

NC

Note 1: Package Not Recommended For New Design

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WF128K32-XXX5

ABSOLUTE MAXIMUM RATINGS (1)

Parameter		Unit
Operating Temperature	-55 to +125	°C
Supply Voltage Range (VCC)	-2.0 to +7.0	V
Signal voltage range (any pin except A9) (2)	-2.0 to +7.0	V
Storage Temperature Range	-65 to +150	°C
Lead Temperature (soldering, 10 seconds)	+300	°C
Data Retention Mil Temp	10 years
Endurance (write/erase cycles) Mil Temp	10,000 cycles min.
A9 Voltage for sector protect (VID) (3)	-2.0 to +14.0	V

NOTES:

1.Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability.

2.Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may overshoot Vss to -2.0 V for periods of up to 20ns. Maximum DC voltage on output and I/O pins is Vcc + 0.5V. During voltage transitions, outputs may overshoot to Vcc + 2.0 V for periods of up to 20ns.

3.Minimum DC input voltage on A9 pin is -0.5V. During voltage transitions, A9 may overshoot Vss to -2V for periods of up to 20ns. Maximum DC input voltage on A9 is +13.5V which may overshoot to 14.0 V for periods up to 20ns.

RECOMMENDED OPERATING CONDITIONS

Parameter	Symbol	Min	Max	Unit
SupplyVoltage	VCC	4.5	5.5	V
Input High Voltage	VIH	2.0	VCC + 0.3	V
Input Low Voltage	VIL	-0.5	+0.8	V
Operating Temp. (Mil.)	TA	-55	+125	°C
A9 Voltage for Sector Protect	VID	11.5	12.5	V

CAPACITANCE

(TA = +25ºC)

	Parameter					Symbol	Conditions	Max	Unit
					capacitance	COE	VIN = 0 V, f = 1.0 MHz	50	pF
	OE
					1-4 capacitance	CWE	VIN = 0 V, f = 1.0 MHz		pF
	WE
					HIP (PGA)			20
					CQFP G2U/G1U/G1T			15
			1-4 capacitance			CCS	VIN = 0 V, f = 1.0 MHz	20	pF
		CS
	Data I/O capacitance					CI/O	VI/O = 0 V, f = 1.0 MHz	20	pF
	Addressinputcapacitance					CAD	VIN = 0 V, f = 1.0 MHz	50	pF

This parameter is guaranteed by design but not tested.

DC CHARACTERISTICS - CMOS COMPATIBLE

(VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C)

Parameter

Symbol

Conditions

Unit

Min

Max

Input Leakage Current

ILI

VCC = 5.5, VIN = GND to VCC

10

µA

OutputLeakageCurrent

ILOx32

VCC = 5.5, VIN = GND to VCC

10

µA

VCC Active Current for Read(1)

ICC1

= VIL,

= VIH

140

mA

CS

OE

VCC Active Current for Program

ICC2

= VIH

200

mA

CS = VIL, OE

or Erase(2)

VCC StandbyCurrent

ICC3

VCC = 5.5,

= VIH, f = 5MHz

6.5

mA

CS

VCC Static Current

ICC4

VCC = 5.5,

= VIH

0.6

mA

CS

OutputLowVoltage

VOL

IOL = 8.0 mA, VCC = 4.5

0.45

V

Output High Voltage

VOH1

IOH = -2.5 mA, VCC = 4.5

0.85 x

V

VCC

Output High Voltage

VOH2

IOH = -100 µA, VCC = 4.5

VCC

V

-0.4

Low VCC Lock Out Voltage

VLKO

3.2

V

NOTES:

1.The ICC current listed includes both the DC operating current and the frequency dependent component (at 5 MHz). The frequency component typically is less than 2 mA/MHz, with OE at VIH.

2.ICC active while Embedded Algorithm (program or erase) is in progress.

3.DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V

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WF128K32-XXX5

AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS, CS CONTROLLED

(VCC = 5.0V, VSS = 0V, TA = -55°C TO+125°C)

Parameter									Symbol			-50				-60				-70				-90				-120				-150			Unit
											Min			Max	Min			Max	Min		Max		Min			Max	Min		Max		Min		Max
		Write Cycle Time							tAVAV	tWC	50				60				70				90				120				150				ns
									tWLEL	tWS	0				0				0				0				0				0				ns
		WE				Setup Time
									tELEH	tCP	25				30				35				45				50				50				ns
		CS		Pulse Width
		Address Setup Time							tAVEL	tAS	0				0				0				0				0				0				ns
		Data Setup Time							tDVEH	tDS	25				30				30				45				50				50				ns
		Data Hold Time							tEHDX	tDH	0				0				0				0				0				0				ns
		Address Hold Time							tELAX	tAH	40				45				45				45				50				50				ns
								High	tEHWH	tWH	0				0				0				0				0				0				ns
		WE			Hold from		WE
									tEHEL	tCPH	20				20				20				20				20				20				ns
		CS	Pulse Width High
		Duration of Programming Operation							tWHWH1		14				14				14				14				14				14				µs
		Duration of Erase Operation							tWHWH2		2.2			60	2.2			60	2.2		60		2.2			60	2.2		60		2.2		60		sec
		Read Recovery before Write							tGHEL		0				0				0				0				0				0				ns
		Chip Programming Time												12.5				12.5			12.5					12.5			12.5				12.5		sec

FIG. 4 AC TEST CIRCUIT							AC TEST CONDITIONS
							Parameter	Typ	Unit
							Input Pulse Levels	VIL = 0, VIH = 3.0	V
							Input Rise and Fall	5	ns
							Input and Output Reference Level	1.5	V
							Output Timing Reference Level	1.5	V
							Notes:
							VZ is programmable from -2V to +7V.
							IOL & IOH programmable from 0 to 16mA.
							Tester Impedance Z0 = 75 ý.
							VZ is typically the midpoint of VOH and VOL.
							IOL & IOH are adjusted to simulate a typical resistive load circuit.
							ATE tester includes jig capacitance.
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WF128K32-XXX5

AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS, WE CONTROLLED

(VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C)

Parameter			Symbol			-50				-60				-70				-90				-120				-150			Unit
					Min			Max	Min			Max	Min			Max	Min			Max	Min		Max		Min		Max
Write Cycle Time			tAVAV	tWC	50				60				70				90				120				150				ns
Chip Select Setup Time			tELWL	tCS	0				0				0				0				0				0				ns
Write Enable Pulse Width			tWLWH	tWP	25				30				35				45				50				50				ns
Address Setup Time			tAVWL	tAS	0				0				0				0				0				0				ns
Data Setup Time			tDVWH	tDS	25				30				30				45				50				50				ns
Data Hold Time			tWHDX	tDH	0				0				0				0				0				0				ns
Address Hold Time			tW L A X	tAH	40				45				45				45				50				50				ns
Chip Select Hold Time			tWHEH	tCH	0				0				0				0				0				0				ns
Write Enable Pulse Width High			tWHWL	tWPH	20				20				20				20				20				20				ns
Duration of Byte Programming Operation (min)			tWHWH1		14				14				14				14				14				14				µs
Sector Erase Time			tWHWH2		2.2			60	2.2			60	2.2			60	2.2			60	2.2		60		2.2		60		sec
Read Recovery Time Before Write			tGHWL		0				0				0				0				0				0				ns
VCC Setup Time				tVCS	50				50				50				50				50				50				µs
Chip Programming Time								12.5				12.5				12.5				12.5			12.5				12.5		sec
Output Enable Setup Time				tOES	0				0				0				0				0				0				ns
Output Enable Hold Time (1)				tOEH	10				10				10				10				10				10				ns

1. For Toggle and Data Polling.

AC CHARACTERISTICS – READ ONLY OPERATIONS

(VCC = 5.0V, VSS = 0V, TA = -55°C TO +125°C)

	Parameter							Symbol			-50				-60				-70				-90				-120				-150			Unit
										Min			Max	Min Max				Min Max				Min Max				Min Max				Min Max
	Read Cycle Time							tAVAV	tRC	50				60				70				90				120				150				ns
	Address Access Time							tAVQV	tACC				50			60				70				90				120				150		ns
	Chip Select Access Time							tELQV	tCE				50			60				70				90				120				150		ns
								tGLQV	tOE				25			30				35				40				50				55		ns
	OE	to Output Valid
	Chip Select to Output High Z (1)							tEHQZ	tDF				20			20				20				25				30				35		ns
								tGHQZ	tDF				20			20				20				25				30				35		ns
	OE		High to Output High Z (1)
									tOH	0				0				0				0				0				0				ns
	Output Hold from Address,			CS	or	OE	Change,	tAXQX
	whichever is first

1. Guaranteed by design, not tested.

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