MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad 3-State
Noninverting Buffers
High±Performance Silicon±Gate CMOS
The MC74HC125A and MC74HC126A are identical in pinout to the LS125 and LS126. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
The HC125A and HC126A noninverting buffers are designed to be used with 3±state memory address drivers, clock drivers, and other bus±oriented systems. The devices have four separate output enables that are active±low (HC125A) or active±high (HC126A).
•Output Drive Capability: 15 LSTTL Loads
•Outputs Directly Interface to CMOS, NMOS, and TTL
•Operating Voltage Range: 2.0 to 6.0 V
•Low Input Current: 1.0 μA
•High Noise Immunity Characteristic of CMOS Devices
•In Compliance with the Requirements Defined by JEDEC Standard No. 7A
•Chip Complexity: 72 FETs or 18 Equivalent Gates
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LOGIC DIAGRAM |
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HC125A |
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HC126A |
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Active±Low Output Enables |
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Active±High Output Enables |
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A1 |
2 |
3 |
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Y1 |
A1 |
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2 |
3 |
Y1 |
1 |
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1 |
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OE1 |
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OE1 |
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A2 |
5 |
6 |
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Y2 |
A2 |
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5 |
6 |
Y2 |
4 |
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4 |
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OE2 |
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OE2 |
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A3 |
9 |
8 |
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Y3 |
A3 |
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9 |
8 |
Y3 |
10 |
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10 |
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OE3 |
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OE3 |
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A4 |
12 |
11 |
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Y4 |
A4 |
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12 |
11 |
Y4 |
13 |
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13 |
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OE4 |
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OE4 |
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PIN 14 = VCC
PIN 7 = GND
FUNCTION TABLE
MC74HC125A
MC74HC126A
N SUFFIX
14±LEAD PLASTIC DIP PACKAGE
CASE 646±06
D SUFFIX
14±LEAD PLASTIC SOIC PACKAGE
CASE 751A±03
DT SUFFIX
14±LEAD PLASTIC TSSOP PACKAGE
CASE 948G±01
ORDERING INFORMATION
MC74HCXXXAN Plastic
MC74HCXXXAD SOIC
MC74HCXXXADT TSSOP
PIN ASSIGNMENT
OE1 |
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1 |
14 |
VCC |
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A1 |
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2 |
13 |
OE4 |
Y1 |
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3 |
12 |
A4 |
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OE2 |
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4 |
11 |
Y4 |
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A2 |
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5 |
10 |
OE3 |
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Y2 |
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6 |
9 |
A3 |
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GND |
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7 |
8 |
Y3 |
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HC125A
Inputs |
Output |
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A |
OE |
Y |
H |
L |
H |
L |
L |
L |
X |
H |
Z |
HC126A
Inputs Output
A OE Y
H H H L H L X L Z
4/97
Motorola, Inc. 1997 |
1 |
REV 8 |
MC74HC125A MC74HC126A
MAXIMUM RATINGS*
Symbol |
Parameter |
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Value |
Unit |
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VCC |
DC Supply Voltage (Referenced to GND) |
± 0.5 to + 7.0 |
V |
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Vin |
DC Input Voltage (Referenced to GND) |
± 0.5 to VCC + 0.5 |
V |
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Vout |
DC Output Voltage (Referenced to GND) |
± 0.5 to VCC + 0.5 |
V |
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Iin |
DC Input Current, per Pin |
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± 20 |
mA |
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Iout |
DC Output Current, per Pin |
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± 35 |
mA |
ICC |
DC Supply Current, VCC and GND Pins |
± 75 |
mA |
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PD |
Power Dissipation in Still Air |
Plastic DIP² |
750 |
mW |
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SOIC Package² |
500 |
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TSSOP Package² |
450 |
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Tstg |
Storage Temperature |
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± 65 to + 150 |
_C |
TL |
Lead Temperature, 1 mm from Case for 10 Seconds |
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_C |
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(Plastic DIP, SOIC or TSSOP Package) |
260 |
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This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the
range GND v (Vin or Vout) v VCC. Unused inputs must always be
tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.
²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C SOIC Package: ± 7 mW/_C from 65_ to 125_C
TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol |
Parameter |
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Min |
Max |
Unit |
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VCC |
DC Supply Voltage (Referenced to GND) |
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2.0 |
6.0 |
V |
Vin, Vout |
DC Input Voltage, Output Voltage |
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0 |
VCC |
V |
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(Referenced to GND) |
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TA |
Operating Temperature, All Package Types |
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± 55 |
+ 125 |
_C |
tr, tf |
Input Rise and Fall Time |
VCC = 2.0 V |
0 |
1000 |
ns |
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(Figure 1) |
VCC = 4.5 V |
0 |
500 |
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VCC = 6.0 V |
0 |
400 |
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DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
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Guaranteed Limit |
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VCC |
± 55 to |
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Symbol |
Parameter |
Test Conditions |
V |
25_C |
v 85_C |
v 125_C |
Unit |
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VIH |
Minimum High±Level Input |
Vout = VCC ± 0.1 V |
2.0 |
1.5 |
1.5 |
1.5 |
V |
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Voltage |
|Iout| v 20 |
μA |
3.0 |
2.1 |
2.1 |
2.1 |
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4.5 |
3.15 |
3.15 |
3.15 |
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6.0 |
4.2 |
4.2 |
4.2 |
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VIL |
Maximum Low±Level Input |
Vout = 0.1 V |
2.0 |
0.5 |
0.5 |
0.5 |
V |
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Voltage |
|Iout| v 20 μA |
3.0 |
0.9 |
0.9 |
0.9 |
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4.5 |
1.35 |
1.35 |
1.35 |
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6.0 |
1.8 |
1.8 |
1.8 |
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VOH |
Minimum High±Level Output |
Vin = VIH |
μA |
2.0 |
1.9 |
1.9 |
1.9 |
V |
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Voltage |
|Iout| v 20 |
4.5 |
4.4 |
4.4 |
4.4 |
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6.0 |
5.9 |
5.9 |
5.9 |
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Vin = VIH |
|Iout| v 3.6 mA |
3.0 |
2.48 |
2.34 |
2.2 |
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|Iout| v 6.0 mA |
4.5 |
3.98 |
3.84 |
3.7 |
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|Iout| v 7.8 mA |
6.0 |
5.48 |
5.34 |
5.2 |
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VOL |
Maximum Low±Level Output |
Vin = VIL |
μA |
2.0 |
0.1 |
0.1 |
0.1 |
V |
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Voltage |
|Iout| v 20 |
4.5 |
0.1 |
0.1 |
0.1 |
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6.0 |
0.1 |
0.1 |
0.1 |
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Vin = VIL |
|Iout| v 3.6 mA |
3.0 |
0.26 |
0.33 |
0.4 |
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|Iout| v 6.0 mA |
4.5 |
0.26 |
0.33 |
0.4 |
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|Iout| v 7.8 mA |
6.0 |
0.26 |
0.33 |
0.4 |
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MOTOROLA |
2 |
High±Speed CMOS Logic Data |
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DL129 Ð Rev 6 |
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