January 1990
Revised September 1998
74ACQ241
Octal Buffer/Line Driver with 3-STATE Outputs
General Description
The ACQ241 is an octal buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter or receiver which provides improved PC board density. The ACQ utilizes Fairchild FACT Quiet Seriesä technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTOä output control and undershoot corrector in addition to a split ground bus for superior performance.
Features
■ICC and IOZ reduced by 50%
■Guaranteed simultaneous switching noise level and dynamic threshold performance
■Guaranteed pin-to-pin skew AC performance
■Improved latch-up immunity
■3-STATE outputs drive bus lines or buffer memory address registers
■Outputs source/sink 24 mA
■Faster prop delays than the standard AC
Ordering Code:
Order Number |
Package Number |
Package Description |
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74ACQ241SC |
M20B |
20-Lead Small Outline Integrated Circuit, JEDEC MS-013, 0.300” Wide Body |
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74ACQ241PC |
N20A |
20-Lead Plastic Dual-In-Line Package, JEDEC MS-001, 0.300” Wide |
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Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol |
Pin Descriptions |
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IEEE/IEC |
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Pin Names |
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Description |
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1, OE2 |
3-STATE Output Enable Inputs |
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OE |
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I0–I7 |
Inputs |
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O0–O7 |
Outputs |
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Truth Tables |
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Inputs |
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Outputs |
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OE1 |
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In |
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(Pins 12, 14, 16, 18) |
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Connection Diagram |
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L |
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L |
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L |
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Pin Assignment for DIP and SOIC |
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L |
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H |
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H |
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H |
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X |
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Z |
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Inputs |
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Outputs |
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OE2 |
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In |
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(Pins 3, 5, 7, 9) |
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H |
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L |
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L |
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H |
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H |
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H |
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H |
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X |
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Z |
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H = HIGH Voltage Level |
X = Immaterial |
L = LOW Voltage Level |
Z = High Impedance |
FACTä, FACT Quiet Seriesä, and GTOä are trademarks of Fairchild Semiconductor Corporation. |
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Outputs STATE-3 with Driver Buffer/Line Octal 74ACQ241
© 1998 Fairchild Semiconductor Corporation |
DS010642.prf |
www.fairchildsemi.com |
74ACQ241
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) |
−0.5V to +7.0V |
DC Input Diode Current (IIK) |
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VI = −0.5V |
−20 mA |
VI = VCC + 0.5V |
+20 mA |
DC Input Voltage (VI) |
−0.5V to VCC + 0.5V |
DC Output Diode Current (IOK) |
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VO = −0.5V |
−20 mA |
VO = VCC + 0.5V |
+20 mA |
DC Output Voltage (VO) |
−0.5V to VCC + 0.5V |
DC Output Source |
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or Sink Current (IO) |
± 50 mA |
DC VCC or Ground Current |
± 50 mA |
per Output Pin (ICC or IGND) |
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Storage Temperature (TSTG) |
−65°C to +150°C |
DC Latch-Up Source or |
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Sink Current |
±300 mA |
Junction Temperature (TJ) |
140°C |
PDIP |
Recommended Operating
Conditions
Supply Voltage (VCC) |
2.0V to 6.0V |
Input Voltage (VI) |
0V to VCC |
Output Voltage (VO) |
0V to VCC |
Operating Temperature (TA) |
−40°C to +85°C |
Minimum Input Edge Rate V/ t |
125 mV/ns |
VIN from 30% to 70% of VCC |
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VCC @ 3.0V, 4.5V, 5.5V |
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Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACTä circuits outside databook specifications.
www.fairchildsemi.com |
2 |
DC Electrical Characteristics
Symbol |
Parameter |
VCC |
TA = +25°C |
TA = −40°C to +85°C |
Units |
Conditions |
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(V) |
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Typ |
Guaranteed Limits |
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VIH |
Minimum High Level |
3.0 |
1.5 |
2.1 |
2.1 |
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VOUT = 0.1V |
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Input Voltage |
4.5 |
2.25 |
3.15 |
3.15 |
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or VCC − 0.1V |
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5.5 |
2.75 |
3.85 |
3.85 |
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VIL |
Maximum Low Level |
3.0 |
1.5 |
0.9 |
0.9 |
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VOUT = 0.1V |
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Input Voltage |
4.5 |
2.25 |
1.35 |
1.35 |
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or VCC − 0.1V |
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5.5 |
2.75 |
1.65 |
1.65 |
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VOH |
Minimum High Level |
3.0 |
2.99 |
2.9 |
2.9 |
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IOUT = −50 μA |
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Output Voltage |
4.5 |
4.49 |
4.4 |
4.4 |
V |
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5.5 |
5.49 |
5.4 |
5.4 |
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VIN = VIL or VIH |
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3.0 |
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2.56 |
2.46 |
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IOH = −12 mA |
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4.5 |
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3.86 |
3.76 |
V |
IOH = −24 mA |
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5.5 |
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4.86 |
4.76 |
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IOH = −24 mA (Note 2) |
VOL |
Maximum Low Level |
3.0 |
0.002 |
0.1 |
0.1 |
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IOUT = 50 μA |
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Output Voltage |
4.5 |
0.001 |
0.1 |
0.1 |
V |
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5.5 |
0.001 |
0.1 |
0.1 |
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VIN = VIL or VIH |
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3.0 |
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0.36 |
0.44 |
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IOL = 12 mA |
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4.5 |
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0.36 |
0.44 |
V |
IOL = 24 mA |
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5.5 |
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0.36 |
0.44 |
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IOL = 24 mA (Note 2) |
IIN |
Maximum Input Leakage Current |
5.5 |
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± 0.1 |
± 1.0 |
μA |
VI = VCC, GND |
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(Note 4) |
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IOLD |
Minimum Dynamic |
5.5 |
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75 |
mA |
VOLD = 1.65V Max |
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Output Current |
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IOHD |
(Note 3) |
5.5 |
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−75 |
mA |
VOHD = 3.85V Min |
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ICC |
Maximum Quiescent |
5.5 |
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4.0 |
40.0 |
μA |
VIN = VCC or GND |
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(Note 4) |
Supply Current |
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IOZ |
Maximum 3-STATE |
5.5 |
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±0.25 |
±2.5 |
μA |
VI (OE) = VIL, VIH |
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Leakage Current |
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VI = VCC, GND |
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VO = VCC, GND |
VOLP |
Quiet Output |
5.0 |
1.1 |
1.5 |
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V |
Figures 1, 2 |
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Maximum Dynamic VOL |
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(Note 5)(Note 6) |
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VOLV |
Quiet Output |
5.0 |
−0.6 |
−1.2 |
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V |
Figures 1, 2 |
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Minimum Dynamic VOL |
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(Note 5)(Note 6) |
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VIHD |
Minimum High Level |
5.0 |
3.1 |
3.5 |
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V |
(Note 5)(Note 7) |
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Dynamic Input Voltage |
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VILD |
Maximum Low Level |
5.0 |
1.9 |
1.5 |
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V |
(Note 5)(Note 7) |
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Dynamic Input Voltage |
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Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
Note 5: DIP package.
Note 6: Max number of outputs defined as (n). Data Inputs are driven 0V to 5V. One output @ GND.
Note 7: Max number of Data Inputs (n) switching. n−1 Inputs switching 0V to 5V . Input-under-test switching: 5V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz.
74ACQ241
3 |
www.fairchildsemi.com |
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