Fairchild Semiconductor FM27C040NE120, FM27C040N90, FM27C040N150, FM27C040N120 Datasheet

February 1999

NM27C040

4,194,304-Bit (512K x 8) High Performance CMOS EPROM

General Description

The NM27C040 is a high performance, 4,194,304-bit Electrically Programmable UV Erasable Read Only Memory. It is organized as 512K words of 8 bits each. Its pin-compatibility with byte-wide JEDEC EPROMs enables upgrades through 8 Mbit EPROMs. The “Don’t Care” feature on VPP during read operations allows memory expansions from 1M to 8 Mbits with no printed circuit board changes.

The NM27C040 provides microprocessor-based systems extensive storage capacity for large portions of operating system and application software. Its 120ns access time provides high speed operation with high-performance CPUs. The NM27C040 offers a single chip solution for the code storage requirements of 100% firmware-based equipment. Frequently used software routines are quickly executed from EPROM storage, greatly enhancing system utility.

The NM27C040 is manufactured using Fairchild’s advanced CMOS AMG™ EPROM technology.

Features

■High performance CMOS

—120, 150ns access time*

■Simplified upgrade path

—VPP is a “Don’t Care” during normal read operation

■Manufacturer’s identification code

■JEDEC standard pin configuration

—32-pin PDIP

—32-pin PLCC

—32-pin CERDIP

*Note: New revision meets 70ns. Please check with factory for availability.

Block Diagram

VCC

GND

VPP

OE

CE/PGM

A0 - A18

Address

Inputs

AMG™ is a trademark of WSI, Inc.

Output Enable,

Chip Enable, and

Program Logic

Y Decoder

X Decoder

. .

. . . . . . .

Data Outputs O0 - O7

Output

Buffers

Y Gating

4,194,304-Bit Cell Matrix

DS010836-1

© 1999 Fairchild Semiconductor Corporation

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NM27C040 Rev. C.1

EPROM CMOS Performance High 8) x (512K Bit-4,194,304 NM27C040

Connection Diagrams

27C080

27C020

27C010

NM27C040

A19

XX/VPP

XX/VPP

XX/VPP

1

32

VCC

A16

A16

A16

A16

2

31

A18

A15

A15

A15

A15

3

30

A17

A12

A12

A12

A12

4

29

A14

A7

A7

A7

A7

5

28

A13

A6

A6

A6

A6

6

27

A8

A5

A5

A5

A5

7

26

A9

A4

A4

A4

A4

8

25

A11

A3

A3

A3

A3

9

24

OE

A2

A2

A2

A2

10

23

A10

A1

A1

A1

A1

11

22

CE/PGM

A0

A0

A0

A0

12

21

O7

O0

O0

O0

O0

13

20

O6

O1

O1

O1

O1

14

19

O5

O2

O2

O2

O2

15

18

O4

GND

GND

GND

GND

16

17

O3

Note: Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27C040 pin.

27C010					27C020					27C080
VCC					VCC					VCC
XX/PGM					XX/PGM					A18
NC					A17					A17
A14					A14					A14
A13					A13					A13
A8					A8						A8
A9					A9						A9
A11					A11					A11
	OE					OE				OE/VPP
A10					A10					A10
					CE				CE/PGM
	CE
O7					O7						O7
O6					O6						O6
O5					O5						O5
O4					O4						O4
O3					O3						O3

DS010836-2

Commercial Temperature Range (0°C to +70°C) VCC = 5V ±10%

Parameter/Order Number	Access Time (ns)
NM27C040 Q, N, V 120	120
NM27C040 Q, N, V 150	150

Pin Names

	A0–A18					Addresses
	CE/PGM					Chip Enable/Program
						Output Enable
		OE
	O0–O7					Outputs
		XX				Don’t Care (During Read)

Extended Temperature Range (-40°C to +85°C) VCC = 5V ±10%

Parameter/Order Number	Access Time (ns)
NM27C040 QE, NE, VE 150	150

Package Types: NM27C040 Q, N,V XXX

Q = Quartz-Windowed Ceramic DIP

N = Plastic DIP

V = PLCC

•All packages conform to the JEDEC standard.

•All versions are guaranteed to function for slower speeds.

EPROM CMOS Performance High 8) x (512K Bit-4,194,304 NM27C040

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NM27C040 Rev. C.1

Absolute Maximum Ratings (Note 1)

Storage Temperature	-65°C to +150°C
All Input Voltages except A9 with
Respect to Ground	-0.6V to +7V
VPP and A9 with Respect to Ground	-0.6V to +14V
VCC Supply Voltage with
Respect to Ground	-0.6V to +7V
ESD Protection	>2000V

All Output Voltages with
Respect to Ground		VCC +1.0V to GND - 0.6V
Operating Range
Range	Temperature	VCC	Tolerance
Commercial	0°C to +70°C	+5V	±10%
Industrial	-40°C to +85°C	+5V	±10%

Read Operation

DC Electrical Characteristics Over operating range with VPP = VCC

Symbol	Parameter			Test Conditions			Min	Max	Units
VIL	Input Low Level						-0.5	0.8	V
VIH	Input High Level						2.0	VCC +1	V
VOL	Output Low Voltage	IOL = 2.1 mA						0.4	V
VOH	Output High Voltage	IOH = -2.5 mA					3.5		V
ISB1	VCC Standby Current (CMOS)		CE	= VCC ± 0.3V				100	μA
ISB2	VCC Standby Current	CE = VIH						1	mA
ICC	VCC Active Current	CE = OE = VIL,				f=5 MHz		30	mA
			I/O = 0 mA
IPP	VPP Supply Current	VPP = VCC						10	μA
VPP	VPP Read Voltage						VCC - 0.4	VCC	V
ILI	Input Load Current	VIN = 5.5V or GND					-1	1	μA
ILO	Output Leakage Current	VOUT = 5.5V or GND					-10	10	μA

AC Electrical Characteristics Over operating range with VPP = VCC

Symbol

Parameter

120

150

Units

Min

Max

Min

Max

tACC

Address to Output Delay

120

150

tCE

120

150

CE

to Output Delay

tOE

OE

to Output Delay

50

50

tDF

Output Disable to

45

55

ns

(Note 2)

Output Float

tOH

Output Hold from Addresses

CE

or

OE

,

0

0

(Note 2)

Whichever Occurred First

Capacitance TA = +25°C, f = 1 MHz (Note 2)

Symbol

Parameter

Conditions

Typ

Max

Units

CIN

Input Capacitance

VIN = 0V

9

15

pF

COUT

Output Capacitance

VOUT = 0V

12

15

pF

EPROM CMOS Performance High 8) x (512K Bit-4,194,304 NM27C040

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NM27C040 Rev. C.1

AC Test Conditions

Output Load	1 TTL Gate and CL = 100 pF (Note 8)
Input Rise and Fall Times		≤5 ns
Input Pulse Levels		0.45V to 2.4V
Timing Measurement Reference Level (Note 10)
Inputs		0.8V and 2V
Outputs`		0.8V and 2V

AC Waveforms (Notes 6, 7, 9)
ADDRESSES	2V		Addresses Valid
	0.8V
CE	2V			tCF
	0.8V
				(Note 4, 5)
			tCE
	2V
OE
	0.8V
				tDF
			tOE
			(Note 3)	(Note 4, 5)
OUTPUT	2V	Hi-Z	Valid Output	Hi-Z
	0.8V
			tACC
				tOH
			(Note 3)
				DS010836-4

Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Note 2: This parameter is only sampled and is not 100% tested.

Note 3: OE may be delayed up to tACC - tOE after the falling edge of CE without impacting tACC.

Note 4: The tDF and tCF compare level is determined as follows:

High to TRI-STATE®, the measured VOH1 (DC) - 0.10V;

Low to TRI-STATE, the measured VOL1 (DC) + 0.10V.

Note 5: TRI-STATE may be attained using OE or CE .

Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 μF ceramic capacitor be used on every device between VCC and GND.

Note 7: The outputs must be restricted to VCC + 1.0V to avoid latch-up and device damage.

Note 8: 1 TTL Gate: IOL = 1.6 mA, IOH = -400 μA.

CL: 100 pF includes fixture capacitance.

Note 9: VPP may be connected to VCC except during programming.

Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns Max.

EPROM CMOS Performance High 8) x (512K Bit-4,194,304 NM27C040

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NM27C040 Rev. C.1