Fairchild Semiconductor 74ACQ374SJX, 74ACQ374SJ, 74ACQ374SCX, 74ACQ374SC, 74ACQ374PC Datasheet

July 1989

Revised November 1999

74ACQ374 • 74ACTQ374

Quiet Series Octal D-Type Flip-Flop with 3-STATE Outputs

General Description

The ACQ/ACTQ374 is a high-speed, low-power octal D- type flip-flop featuring separate D-type inputs for each flipflop and 3-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops.

The ACQ/ACTQ374 utilizes FACT Quiet Series technology to guarantee quiet output switching and improve dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector in addition to a split ground bus for superior performance.

Features

■ICC and IOZ reduced by 50%

■Guaranteed simultaneous switching noise level and dynamic threshold performance

■Guaranteed pin-to-pin skew AC performance

■Improved latch-up immunity

■Buffered positive edge-triggered clock

■3-STATE outputs drive bus lines or buffer memory address registers

■Outputs source/sink 24 mA

■Faster prop delays than the standard AC/ACT374

Ordering Code:

Order Number	Package Number	Package Description
74ACQ374SC	M20B	20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACQ374SJ	M20D	20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACQ374PC	N20A	20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACTQ374SC	M20B	20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACTQ374SJ	M20D	20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACTQ374QSC	MQA20	20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150” Wide
74ACTQ374PC	N20A	20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram	Pin Descriptions
		Pin Names			Description
			D0–D7		Data Inputs
			CP		Clock Pulse Input
					3-STATE Output Enable Input
			OE
			O0–O7		3-STATE Outputs

FACT

, Quiet Series

, FACT Quiet Series

, and GTO are trademarks of Fairchild Semiconductor Corporation.

Outputs STATE-3 with Flop-Flip Type-D Octal Series Quiet 74ACTQ374 • 74ACQ374

© 1999 Fairchild Semiconductor Corporation

DS010238

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74ACQ374 • 74ACTQ374

Logic Symbols

IEEE/IEC

Logic Diagram

Functional Description

The ACQ/ACTQ374 consists of eight edge-triggered flipflops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops.

Truth Table

		Inputs					Outputs
	Dn		CP		OE		On
	H				L		H
	L				L		L
	X		X		H		Z
H = HIGH Voltage		Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance

= LOW-to-HIGH Transition

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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Absolute Maximum Ratings(Note 1)

Supply Voltage (VCC)		− 0.5V to + 7.0V
DC Input Diode Current (IIK)
VI =	− 0.5V	− 20 mA
VI =	VCC + 0.5V	+ 20 mA
DC Input Voltage (VI)		− 0.5V to VCC + 0.5V
DC Output Diode Current (IOK)
VO =	− 0.5V	− 20 mA
VO =	VCC + 0.5V	+ 20 mA
DC Output Voltage (VO)		− 0.5V to VCC + 0.5V
DC Output Source
or Sink Current (IO)		± 50 mA
DC VCC or Ground Current
per Output Pin (ICC or IGND)		± 50 mA
Storage Temperature (TSTG)		− 65° C to + 150° C
DC Latch-Up Source or Sink Current		± 300 mA
Junction Temperature (TJ)
PDIP		140° C

Recommended Operating

Conditions

Supply Voltage (VCC)
ACQ	2.0V to 6.0V
ACTQ	4.5V to 5.5V
Input Voltage (VI)	0V to VCC
Output Voltage (VO)	0V to VCC
Operating Temperature (TA)	− 40° C to + 85° C
Minimum Input Edge Rate ∆ V/∆ t
ACQ Devices
VIN from 30% to 70% of VCC
VCC @ 3.0V, 4.5V, 5.5V	125 mV/ns
Minimum Input Edge Rate ∆ V/∆ t
ACTQ devices
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V	125 mV/ns

Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.

DC Electrical Characteristics for ACQ

Symbol	Parameter	VCC	TA = + 25° C		TA = − 40° C to + 85° C	Units			Conditions
		(V)	Typ	Guaranteed Limits
VIH	Minimum HIGH Level	3.0	1.5	2.1	2.1		VOUT =		0.1V
	Input Voltage	4.5	2.25	3.15	3.15	V	or VCC −			0.1V
		5.5	2.75	3.85	3.85
VIL	Maximum LOW Level	3.0	1.5	0.9	0.9		VOUT =		0.1V
	Input Voltage	4.5	2.25	1.35	1.35	V	or VCC −			0.1V
		5.5	2.75	1.65	1.65
VOH	Minimum HIGH Level	3.0	2.99	2.9	2.9
	Output Voltage	4.5	4.49	4.4	4.4	V	IOUT =		−	50 µ A
		5.5	5.49	5.4	5.4
							VIN =	VIL or VIH
		3.0		2.56	2.46		IOH =	−	12 mA
		4.5		3.86	3.76	V	IOH =	−	24 mA
		5.5		4.86	4.76		IOH =	− 24 mA (Note 2)
VOL	Maximum LOW Level	3.0	0.002	0.1	0.1
	Output Voltage	4.5	0.001	0.1	0.1	V	IOUT =		50 µ A
		5.5	0.001	0.1	0.1
		3.0		0.36	0.44		IOL =	12 mA
		4.5		0.36	0.44	V	IOL =	24 mA
		5.5		0.36	0.44		IOL =	24 mA (Note 2)
IIN (Note 4)	Maximum Input Leakage Current	5.5		± 0.1	± 1.0	µ A	VI =	VCC, GND
IOLD	Minimum Dynamic	5.5			75	mA	VOLD =		1.65V Max
IOHD	Output Current (Note 3)	5.5			− 75	mA	VOHD =			3.85V Min
ICC (Note 4)	Maximum Quiescent Supply Current	5.5		4.0	40.0	µ A	VIN =	VCC or GND
IOZ	Maximum 3-STATE						VI (OE) = VIL, VIH
	Leakage Current	5.5		± 0.25	± 2.5	µ A	VI =	VCC, GND
							VO =	VCC, GND
VOLP	Quiet Output	5.0	1.1	1.5		V	Figure 1, Figure 2
	Maximum Dynamic VOL						(Note 5)(Note 6)

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74ACQ374 • 74ACTQ374

DC Electrical Characteristics for ACQ (Continued)

Symbol	Parameter	VCC	TA = + 25° C		TA = − 40° C to + 85° C	Units	Conditions
		(V)	Typ	Guaranteed Limits
VOLV	Quiet Output	5.0	− 0.6	− 1.2		V	Figure 1, Figure 2
	Minimum Dynamic VOL						(Note 5)(Note 6)
VIHD	Minimum HIGH Level	5.0	3.1	3.5		V	(Note 5)(Note 7)
	Dynamic Input Voltage
VILD	Maximum LOW Level	5.0	1.9	1.5		V	(Note 5)(Note 7)
	Dynamic Input Voltage

Note 2: All outputs loaded; thresholds on input associated with output under test.

Note 3: Maximum test duration 2.0 ms, one output loaded at a time.

Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.

Note 5: DIP Package.

Note 6: Max number of outputs defined as (n). Data inputs are driven 0V to 5V. One output @ GND.

Note 7: Max number of data inputs (n) switching. (n− 1) inputs switching 0V to 5V (ACQ). Input-under-test switching: 5V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz.

DC Electrical Characteristics for ACTQ

Symbol	Parameter	VCC	TA = + 25° C		TA = − 40° C to + 85° C		Units		Conditions
		(V)	Typ	Guaranteed Limits
VIH	Minimum HIGH Level	4.5	1.5	2.0		2.0	V	VOUT =		0.1V
	Input Voltage	5.5	1.5	2.0		2.0		or VCC −			0.1V
VIL	Maximum LOW Level	4.5	1.5	0.8		0.8	V	VOUT =		0.1V
	Input Voltage	5.5	1.5	0.8		0.8		or VCC −			0.1V
VOH	Minimum HIGH Level	4.5	4.49	4.4		4.4	V	IOUT =		−	50 µ A
	Output Voltage	5.5	5.49	5.4		5.4
								VIN =	VIL or VIH
		4.5		3.86	3.76		V	IOH =	−	24 mA
		5.5		4.86	4.76			IOH =	− 24 mA (Note 8)
VOL	Maximum LOW Level	4.5	0.001	0.1		0.1	V	IOUT =		50 µ A
	Output Voltage	5.5	0.001	0.1		0.1
								VIN =	VIL or VIH
		4.5		0.36	0.44		V	IOL =	24 mA
		5.5		0.36	0.44			IOL =	24 mA (Note 8)
IIN (Note 4)	Maximum Input Leakage Current	5.5		± 0.1	±	1.0	µ A	VI =	VCC, GND
IOZ	Maximum 3-STATE	5.5		± 0.25	±	2.5	µ A	VI =	VIL, VIH
	Current							VO =	VCC, GND
ICCT	Maximum	5.5	0.6			1.5	mA	VI =	VCC − 2.1V
	ICC/Input (Note 4)
IOLD	Minimum Dynamic	5.5				75	mA	VOLD =		1.65V Max
IOHD	Output Current (Note 8)	5.5			− 75		mA	VOHD =			3.85V Min
ICC	Maximum Quiescent	5.5		4.0	40.0		µ A	VIN =	VCC
(Note 4)	Supply Current							or GND
VOLP	Quiet Output	5.0	1.1	1.5			V	Figure 1, Figure 2
	Maximum Dynamic VOL							(Note 10)(Note 11)
VOLV	Quiet Output	5.0	− 0.6	− 1.2			V	Figure 1, Figure 2
	Minimum Dynamic VOL							(Note 10)(Note 11)
VIHD	Minimum HIGH Level Dynamic Input Voltage	5.0	1.9	2.2			V	(Note 10)(Note 12)
VILD	Maximum LOW Level Dynamic Input Voltage	5.0	1.2	0.8			V	(Note 10)(Note 12)

Note 8: All outputs loaded; thresholds on input associated with output under test.

Note 9: Maximum test duration 2.0 ms, one output loaded at a time.

Note 10: DIP package.

Note 11: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND

Note 12: Max number of data inputs (n) switching. (n− 1) inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz.

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