Siemens HYB3116400BJ-50, HYB3116400BJ-60, HYB3116400BT-50, HYB3116400BT-60, HYB3117400BJ-50 Datasheet

Semiconductor Group 1 1998-10-01

• 4 194 304 words by 4-bit organization

• 0 to 70 °C operating temperature

• Fast Page Mode operation

• Performance:

• Power Dissipation, Refresh & Addressing:

• Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh

and test mode

• All inputs, outputs and clocks fully TTL (5 V versions) and LV-TTL (3.3 V version)-compatible

• Plastic Package: P-SOJ-26/24-1 300 mil

P-TSOPII-26/24-1 300 mil

-50 -60

t

RAC

RAS access time 50 60 ns

t

CAC

CAS access time 13 15 ns

t

AA

Access time from address 25 30 ns

t

RC

Read/Write cycle time 84 104 ns

t

PC

Fast page mode cycle time 35 40 ns

HYB 5116400 HYB 3116400 HYB 5117400 HYB 3117400

-50 -60 -50 -60 -50 -60 -50 -60

Power Supply 5 V ± 10% 3.3 V ± 0.3 V 5 V ± 10% 3.3 V ± 0.3 V

Addressing 12/10 12/10 11/11 11/11

Refresh 4096 cycles / 64 ms 2048 cycles / 32 ms

Active 275 220 180 144 440 385 288 252 mW

TTL Standby 11 7.2 11 7.2 mW

CMOS Standby 5.5 3.6 5.5 3.6 mW

4M × 4-Bit Dynamic RAM

2k & 4k Refresh

(Fast Page Mode)

Advanced Information

HYB 5116400BJ-50/-60

HYB 5117400BJ-50/-60

HYB 3116400BJ/BT-50/-60

HYB 3117400BJ-50/-60

HYB 5116(7)400BJ-50/-60

HYB 3116(7)400BJ/BT-50/-60

4M × 4 DRAM

Semiconductor Group 2 1998-10-01

The HYB 5(3)116(7)400 are 16 MBit dynamic RAMs based on die revisions “G” & “F” and organized

as 4 194 304 words by 4-bits. The HYB 5(3)116(7)400BJ/BT utilizes a submicron CMOS silicon

gate process technology, as well as advanced circuit techniques to provide wide operating margins,

both internally and for the system user. Multiplexed address inputs permit the HYB 5(3)116(7)400

to be packaged in a standard SOJ-26/24 and TSOPII-26/24 plastic package with 300 mil width.

These packages provide high system bit densities and are compatible with commonly used

automatic testing and insertion equipment.

Ordering Information

Type Ordering Code Package Descriptions

2k-Refresh Versions

HYB 5117400BJ-50 Q67100-Q1086 P-SOJ-26/24-1 300 mil 5 V 50 ns FPM-DRAM

HYB 5117400BJ-60 Q67100-Q1087 P-SOJ-26/24-1 300 mil 5 V 60 ns FPM-DRAM

HYB 3117400BJ-50 on request P-SOJ-26/24-1 300 mil 3.3 V 50 ns FPM-DRAM

HYB 3117400BJ-60 on request P-SOJ-26/24-1 300 mil 3.3 V 60 ns FPM-DRAM

4k-Refresh Versions

HYB 5116400BJ-50 Q67100-Q1049 P-SOJ-26/24-1 300 mil 5 V 50 ns FPM-DRAM

HYB 5116400BJ-60 Q67100-Q1050 P-SOJ-26/24-1 300 mil 5 V 60 ns FPM-DRAM

HYB 3116400BJ-50 on request P-SOJ-26/24-1 300 mil 3.3 V 50 ns FPM-DRAM

HYB 3116400BJ-60 on request P-SOJ-26/24-1 300 mil 3.3 V 60 ns FPM-DRAM

HYB 3116400BT-50 on request P-TSOPII-26/24-1 300 mil 3.3 V 50 ns FPM-DRAM

HYB 3116400BT-60 on request P-TSOPII-26/24-1 300 mil 3.3 V 60 ns FPM-DRAM

HYB 5116(7)400BJ-50/-60

HYB 3116(7)400BJ/BT-50/-60

4M × 4 DRAM

Semiconductor Group 3 1998-10-01

Pin Configuration

Pin Names

HYB 5(3)116400

4k-Refresh

HYB 5(3)117400

2k-Refresh

Row Address Inputs A0 - A11 A0 - A10

Column Address Inputs A0 - A9 A0 - A10

Row Address Strobe RAS

Column Address Strobe CAS

Output Enable OE

Data Input/Output I/O1 - I/O4

Read/Write Input WE

Power Supply V

CC

Ground (0 V) V

SS

Not Connected – N.C.

P-SOJ-26/24-1 300 mil

P-TSOPII-26/24-1 300 mil

CC

V

A0 9

10

12

11

2

3

4

5

1

13 14

26

18

17

16

15

22

23

24

25

SPP03454

6

819

21

A10

SS

V

A4

I/O3

I/O4

CAS

OE

SS

V

I/O1

A11 / N.C.

RAS

WE

V

CC

I/O2

A1

A2

A3

A5

A6

A7

A8

A9

HYB 5116(7)400BJ-50/-60

HYB 3116(7)400BJ/BT-50/-60

4M × 4 DRAM

Semiconductor Group 4 1998-10-01

Block Diagram for HYB 5(3)116400 (4k-refresh)

SPB03455

&

No.2 Clock

Generator

Address

Column

Buffers (10)

Controller

Refresh

Refresh

Counter (12)

Buffers (12)

Row

Address

Generator

No.1 Clock

12

10

A0

A1

A2

A3

A4

A5

A6

A7

A8

12

Row

Decoder

RAS

4096 x 1024 x 4

Memory Array

4096

1024

x 4

Sense Amplifier

I/O Gating

10

Column

Decoder

Buffer

Data IN

Data OUT

Buffer

I/O1

4

4

OE

Voltage Down

V

CC

V

CC

12

4

A9

(internal)

Generator

CAS

WE

A10

I/O2

I/O3 I/O4

A11

HYB 5116(7)400BJ-50/-60

HYB 3116(7)400BJ/BT-50/-60

4M × 4 DRAM

Semiconductor Group 5 1998-10-01

Block Diagram for HYB 5(3)117400 (2k-refresh)

Data In

Buffer

Data Out

Buffer

I/O1 I/O2 I/O4

OE

Column

Decoder

Sense Amplifier

I/O Gating

&

No.2 Clock

Generator

Column

Address

Buffers (11)

Refresh

Controller

Refresh

Counter (11)

Buffers (11)

Address

Row

No.1 Clock

Generator

11

Memory Array

Decoder

Row

2048

.

.

.

.

.

.

2048

.

.

.

.

.

.

4

4

4

11

11

WE

CAS

RAS

11

2048 2048x

4

x

x4

I/O3

(internal)

V

Generator

Voltage Down

CC

CC

V

SPB02823

11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

HYB 5116(7)400BJ-50/-60

HYB 3116(7)400BJ/BT-50/-60

4M × 4 DRAM

Semiconductor Group 6 1998-10-01

Absolute Maximum Ratings

Operating temperature range ........................................................................................... 0 to 70 °C

Storage temperature range........................................................................................ – 55 to 150 °C

Input/output voltage (5 V versions)................................................... – 0.5 to min (V

CC

+ 0.5, 7.0) V

Input/output voltage (3.3 V versions)................................................ – 0.5 to min (V

CC

+ 0.5, 4.6) V

Power supply voltage (5 V versions) ....................................................................... – 1.0 V to 7.0 V

Power supply voltage (3.3 V versions) .................................................................... – 1.0 V to 4.6 V

Power dissipation( 5 V versions) .............................................................................................1.0 W

Power dissipation (3.3 V versions) ..........................................................................................0.5 W

Data out current (short circuit) ................................................................................................ 50 mA

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent

damage of the device. Exposure to absolute maximum rating conditions for extended periods

may affect device reliability.

DC Characteristics

T

A

= 0 to 70 °C, V

SS

= 0 V, t

T

= 2 ns

Parameter Symbol Limit Values Unit Test

Condition

min. max.

5 V Versions

Power supply voltage V

CC

4.5 5.5 V

Input high voltage V

IH

2.4 V

CC

+ 0.5 V

1

Input low voltage V

IL

– 0.5 0.8 V

1

Output high voltage (I

OUT

= – 5 mA) V

OH

2.4 – V

1

Output low voltage (I

OUT

= 4.2 mA) V

OL

– 0.4 V

1

3.3 V Versions

Power supply voltage V

CC

3.0 3.6 V

Input high voltage V

IH

2.0 V

CC

+ 0.5 V

1

Input low voltage V

IL

– 0.5 0.8 V

1

TTL Output high voltage (I

OUT

= – 2 mA) V

OH

2.4 – V

1

TTL Output low voltage (I

OUT

= 2 mA) V

OL

– 0.4 V

1

CMOS Output high voltage (I

OUT

= – 100 µA) V

OH

V

CC

– 0.2 – V

CMOS Output low voltage (I

OUT

= 100 µA) V

OL

– 0.2 V

HYB 5116(7)400BJ-50/-60

HYB 3116(7)400BJ/BT-50/-60

4M × 4 DRAM

Semiconductor Group 7 1998-10-01

DC Characteristics (cont’d)

T

A

= 0 to 70 °C, V

SS

= 0 V, t

T

= 2 ns

Parameter Symbol Limit Values Unit Notes

min. max.

2k 4k

Common Parameters

Input leakage current

(0 V ≤ V

IH

≤ V

CC

+ 0.3 V, all other pins = 0 V)

I

I(L)

–10 10 µA

1

Output leakage current

(DO is disabled, 0 V ≤ V

OUT

≤ V

CC

+ 0.3 V)

I

O(L)

–10 10 µA

1

Average V

CC

supply current

-50 ns version

-60 ns version

(RAS, CAS, address cycling: t

RC

= t

RC MIN.

)

I

CC1

–

–

80

70

50

40

mA

mA

2, 3, 4

2, 3, 4

Standby V

CC

supply current (RAS = CAS = V

IH

) I

CC2

– 2 mA –

AverageV

CC

supply current, duringRAS-only refresh

cycles -50 ns version

-60 ns version

(RAS cycling, CAS = V

IH

, t

RC

= t

RC MIN.

)

I

CC3

–

–

80

70

50

40

mA

mA

2, 4

2, 4

Average V

CC

supply current,during fast page mode

-50 ns version

-60 ns version

(RAS = V

IL

, CAS, address cycling: t

PC

= t

PC MIN.

)

I

CC4

–

–

25

20

mA

mA

2, 3, 4

2, 3, 4

Standby V

CC

supply current

(RAS = CAS = V

CC

– 0.2 V)

I

CC5

–1mA

1

AverageV

CC

supply current, duringCAS-before-RAS

refresh mode -50 ns version

-60 ns version

(RAS, CAS cycling: t

RC

= t

RC MIN.

)

I

CC6

–

–

80

70

50

40

mA

mA

2, 4

2, 4

HYB 5116(7)400BJ-50/-60

HYB 3116(7)400BJ/BT-50/-60

4M × 4 DRAM

Semiconductor Group 8 1998-10-01

Capacitance

T

A

= 0 to 70 °C, f = 1 MHz

Parameter Symbol Limit Values Unit

min. max.

Input capacitance (A0 to A11) C

I1

–5pF

Input capacitance (RAS, CAS, WE, OE) C

I2

–7pF

I/O capacitance (I/O1 - I/O4) C

IO

–7pF

AC Characteristics

5, 6

T

A

= 0 to 70 °C, V

CC

= 5 V ± 10 % / V

CC

= 3.3 V ± 0.3 V, t

T

= 5 ns

Parameter Symbol Limit Values Unit Note

-50 -60

min. max. min. max.

Common Parameters

Random read or write cycle time t

RC

90 – 110 – ns

RAS precharge time t

RP

30 – 40 – ns

RAS pulse width t

RAS

50 10k 60 10k ns

CAS pulse width t

CAS

13 10k 15 10k ns

Row address setup time t

ASR

0–0–ns

Row address hold time t

RAH

8 – 10 – ns

Column address setup time t

ASC

0–0–ns

Column address hold time t

CAH

10 – 15 – ns

RAS to CAS delay time t

RCD

18 37 20 45

RAS to column address delay time t

RAD

13 25 15 30 ns

RAS hold time t

RSH

13 15 – ns

CAS hold time t

CSH

50 60 – ns

CAS to RAS precharge time t

CRP

5–5–ns

Transition time (rise and fall) t

T

3 50 3 50 ns

7

Refresh period for 2k refresh version t

REF

– 32 – 32 ms

Refresh period for 4k refresh version t

REF

– 64 – 64 ms

Read Cycle

Access time from RAS t

RAC

– 50 – 60 ns

8, 9

Access time from CAS t

CAC

– 13 – 15 ns

8, 9

Access time from column address t

AA

– 25 – 30 ns

8, 10