Siemens HYB3164400AJ-50, HYB3164400AJ-60, HYB3164400AT-40, HYB3164400AT-50, HYB3164400AT-60 Datasheet

16M x 4-Bit Dynamic RAM	HYB 3164400AJ/AT(L) -40/-50/-60
(4k & 8k Refresh)	HYB 3165400AJ/AT(L) -40/-50/-60

Advanced Information

•16 777 216 words by 4-bit organization

•0 to 70 °C operating temperature

•Fast Page Mode operation

•Performance:

						-40	-50	-60
tRAC					access time	40	50	60	ns
			RAS
tCAC					access time	10	13	15	ns
		CAS
tAA		Access time from address				20	25	30	ns
tRC		Read/write cycle time				75	90	110	ns
tPC		Fast page mode cycle time				30	35	40	ns

•Single + 3.3 V (± 0.3V) power supply

•Low power dissipation:

max. 396 mW active ( HYB 3164400AJ/AT(L) -40) max. 324 mW active ( HYB 3164400AJ/AT(L) -50) max. 270 mW active ( HYB 3164400AJ/AT(L) -60)

max. 558 mW active ( HYB 3165400AJ/AT(L) -40) max. 468 mW active ( HYB 3165400AJ/AT(L) -50) max. 378 mW active ( HYB 3165400AJ/AT(L) -60)

7.2mW standby (LVTTL)

3.24 mW standby (LVCMOS)

720 μW standby for L-versions

•Read, write, read-modify-write, CAS-before-RAS refresh (CBR), RAS-only refresh, hidden refresh and self refresh (L-version only)

•8192 refresh cycles/128 ms , 13 R/ 11C addresses (HYB 3164400AJ/AT)

4096 refresh cycles/ 64 ms , 12 R/ 12C addresses (HYB 3165400AJ/AT)

•256 msec refresh period for L-versions

•Plastic Package

P-SOJ-32-1	400 mil	HYB 3164(5)400AJ
P-TSOPII-32-1	400 mil	HYB 3164(5)400AT

Semiconductor Group

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6.97

HYB3164(5)400AJ/AT(L)-40/-50/-60 16M x 4-DRAM

This device is a 64 MBit dynamic RAM organized 16 777 216 by 4 bits. The device is fabricated on an advanced second generation 64Mbit 0,35 μm-CMOS silicon gate process technology. The circuit and process design allow this device to achieve high performance and low power dissipation. This DRAM operates with a single 3.3 +/-0.3V power supply and interfaces with either LVTTL or LVCMOS levels. Multiplexed address inputs permit the HYB 3164(5)400AJ/AT to be packaged in a 400mil wide SOJ-32 or TSOP-32 plastic package. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. The HYB3164(5)400ATL parts (L-versions) have a very low power „sleep mode“ supported by Self Refresh

Ordering Information

	Type						Ordering	Package		Descriptions
							Code
	HYB 3164400AJ-40							P-SOJ-32-1	400 mil	DRAM (access time 40 ns)
	HYB 3164400AJ-50							P-SOJ-32-1	400 mil	DRAM (access time 50 ns)
	HYB 3164400AJ-60							P-SOJ-32-1	400 mil	DRAM (access time 60 ns)
	HYB 3164400AT-40							P-TSOPII-32-1	400 mil	DRAM (access time 40 ns)
	HYB 3164400AT-50							P-TSOPII-32-1	400 mil	DRAM (access time 50 ns)
	HYB 3164400AT-60							P-TSOPII-32-1	400 mil	DRAM (access time 60 ns)
	HYB 3165400AJ-40							P-SOJ-32-1	400 mil	DRAM (access time 40 ns)
	HYB 3165400AJ-50							P-SOJ-32-1	400 mil	DRAM (access time 50 ns)
	HYB 3165400AJ-60							P-SOJ-32-1	400 mil	DRAM (access time 60 ns)
	HYB 3165400AT-40							P-TSOPII-32-1	400 mil	DRAM (access time 40 ns)
	HYB 3165400AT-50							P-TSOPII-32-1	400 mil	DRAM (access time 50 ns)
	HYB 3165400AT-60							P-TSOPII-32-1	400 mil	DRAM (access time 60 ns)
	HYB 3164(5)400ATL							P-TSOPII-32-1	400 mil	Low Power DRAMs
	Pin Names
	A0-A12					Address Inputs for 8k-refresh versions HYB 3164400AJ/AT(L)
	A0-A11					Address Inputs for 4k-refresh versions HYB 3165400AJ/AT(L)
						Row Address Strobe
	RAS
						Output Enable
	OE
I/O1-I/O4						Data Input/Output
						Column Address Strobe
CAS
						Read/Write Input
WE
Vcc						Power Supply ( + 3.3V)
Vss						Ground

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HYB3164(5)400AJ/AT(L)-40/-50/-60 16M x 4-DRAM

P-SOJ-32-1 (400 mil)

P-TSOPII-32-1 (400 mil)

O

	VCC				1	32	VSS
		I/O1			2	31	I/O4
		I/O2			3	30	I/O3
		N.C.			4	29	N.C.
	N.C.				5	28	N.C.
		N.C.			6	27	N.C.
						26
		N.C.			7			CAS
					8	25
	WRITE								OE
		RAS			9	24		A12 / N.C. *
.
		A0			10	23			A11
		A1			11	22			A10
		A2			12	21			A9
		A3			13	20			A8
		A4			14	19			A7
		A5			15	18			A6
		VCC			16	17		VSS

* Pin 24 is A12 for HYB 3164400AJ/AT(L) and N.C. for HYB 3165400AJ/AT(L)

Pin Configuration

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HYB3164(5)400AJ/AT(L)-40/-50/-60 16M x 4-DRAM

TRUTH TABLE

FUNCTION

RAS

CAS

WE

OE

ROW

COL

I/O1-

ADDR

ADDR

I/O4

Standby

H

H - X

X

X

X

X

High Impedance

Read

L

L

H

L

ROW

COL

Data Out

Early-Write

L

L

L

X

ROW

COL

Data In

Delayed-Write

L

L

H - L

H

ROW

COL

Data In

Read-Modify-Write

L

L

H - L

L - H

ROW

COL

Data Out, Data In

Fast Page Mode Read

1st Cycle

L

H - L

H

L

ROW

COL

Data Out

2nd Cycle

L

H - L

H

L

n/a

COL

Data Out

Fast Page Mode Early

1st Cycle

L

H - L

L

X

ROW

COL

Data In

Write

2nd Cycle

L

H - L

L

X

n/a

COL

Data In

Fast Page Mode RMW

1st Cycle

L

H - L

H - L

L - H

ROW

COL

Data Out, Data In

2st Cycle

L

H - L

H - L

L - H

n/a

COL

Data Out, Data In

RAS only refresh

L

H

X

X

ROW

n/a

High Impedance

CAS-before-RAS refresh

H - L

L

H

X

X

n/a

High Impedance

Test Mode Entry

H - L

L

L

X

X

n/a

High Impedance

Hidden Refresh

READ

L-H-L

L

H

L

ROW

COL

Data Out

WRITE

L-H-L

L

L

X

ROW

COL

Data In

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			HYB3164(5)400AJ/AT(L)-40/-50/-60
				16M x 4-DRAM
			I/O1 I/O2	I/O4
WE
CAS .	&		Data in	Data out
					OE
			Buffer	Buffer
	No. 2 Clock			4
	Generator		4
12	Column
	Address		12	Column
A0	Buffer(12)			Decoder
A1
A2
A3	Refresh			Sense Amplifier	4
A4	Controller
				I/O Gating
A5
A6
A7	Refresh			4096
A8	Counter (12)
				x4
A9
	12
A10
A11	Row		Row	Memory Array
12	Address	12	Decoder 4096	4096 x 4096 x 4
	Buffers(12)
RAS	No. 1 Clock
	Generator

Block Diagram for HYB 3165400AJ/AT(L)

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				HYB3164(5)400AJ/AT(L)-40/-50/-60
					16M x 4-DRAM
				I/O1 I/O2	I/O4
	WE
CAS .		&		Data in	Data out
						OE
				Buffer	Buffer
		No. 2 Clock			4
		Generator		4
	11	Column
		Address		11	Column
A0		Buffer(11)			Decoder
A1
A2
A3		Refresh			Sense Amplifier	4
A4		Controller
					I/O Gating
A5
A6
A7		Refresh			2048
A8		Counter (13)
					x4
A9
		13
A10
A11		Row		Row	Memory Array
A12	13	Address	13	Decoder 8192	8192 x 2048 x 4
		Buffers(13)
	RAS	No. 1 Clock
		Generator

Block Diagram for HYB 3164400AJ/AT(L)

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HYB3164(5)400AJ/AT(L)-40/-50/-60 16M x 4-DRAM

Absolute Maximum Ratings
Operating temperature range..............................................................................................	0 to 70 °C
Storage temperature range.........................................................................................	– 55 to 150 ° C
Input/output voltage..................................................................................	-0.5 to min (Vcc+0.5,4.6) V
Power supply voltage....................................................................................................	-0.5V to 4.6 V
Power dissipation......................................................................................................................	1.0 W
Data out current (short circuit)..................................................................................................	50 mA
Note

Stresses above those listed under „Absolute Maximum Ratings“ may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may effect device reliability.

DC Characteristics

TA = 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V

Parameter	Symbol	Limit Values		Unit	Note
		min.	max.
Input high voltage	VIH	2.0	Vcc+0.3	V	1)
Input low voltage	VIL	– 0.3	0.8	V	1)
Output high voltage (LVTTL)	VOH	2.4	–	V
Output „H“ level voltage (Iout = -2mA)
Output low voltage (LVTTL)	VOL	–	0.4	V
Output „L“level voltage (Iout = +2mA)
Output high voltage (LVCMOS)	VOH	Vcc-0.2	-	V
Output „H“ level voltage (Iout = -100uA)
Ouput low voltage (LVCMOS)	VOL	-	0.2	V
Output „L“ level voltage (Iout = +100uA)
Input leakage current,any input	II(L)	– 2	2	μA
(0 V < Vin < Vcc , all other pins = 0 V
Output leakage current	IO(L)	– 2	2	μA
(DO is disabled, 0 V < Vout < Vcc )

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HYB3164(5)400AJ/AT(L)-40/-50/-60 16M x 4-DRAM

DC-Characteristics (cont’d)

TA = 0 to 70 °C, VSS = 0 V, VCC = 3.3 V ± 0.3 V

Parameter

Symbol

refresh

version

Unit

Note

4k

8k

Operating Current

-40 ns version

ICC1

155

110

mA

2) 3) 4)

-50 ns version

130

90

mA

-60 ns version

105

75

mA

address cycling: tRC = tRC min.)

(RAS,

CAS,

Standby Current

ICC2

2

2

mA

–

(RAS=CAS= Vih)

RASOnlyRefreshCurrent:

ICC3

110

mA

2) 4)

-

-40 ns version

155

-50ns version

130

90

mA

-60 ns version

105

75

mA

(RAS cycling: CAS = VIH: tRC = tRC min.)

Fast Page Mode Current:

ICC4

-40 ns version

70

70

mA

2) 3) 4)

-50 ns version

60

60

mA

-60 ns version

50

50

mA

= VIL,

address cycling: tPC=tPC min.)

(RAS

CAS,

Standby Current

ICC5

900

900

μA

–

(RAS=CAS= Vcc-0.2V)

Standby Current

(L-Version)

ICC5

200

200

μA

–

(RAS=CAS= Vcc-0.2V)

Before

Refresh Current

ICC6

CAS

RAS

-40 ns version

155

155

mA

2) 4)

-50 ns version

130

130

mA

-60 ns version

105

105

mA

cycling: tRC = tRC min.)

(RAS,

CAS

Self Refresh Current (L-version only)

ICC7

400

400

μA

(CBR cycle with tRAS>TRASSmin,

held low,

CAS

WE

= Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V)

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